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PRELIMINARY DATA SHEET
256M bits DDR2 SDRAM for HYPER DIMM
EDE2508AASE-DF, -BE, -AE (32M words x 8 bits) EDE2516AASE-DF, -BE, -AE (16M words x 16 bits)
Description
The EDE2508AA is a 256M bits DDR2 SDRAM organized as 8,388,608 words x 8 bits x 4 banks. It is packaged in 64-ball FBGA package. The EDE2516AA is a 256M bits DDR2 SDRAM organized as 4,194,304 words x 16 bits x 4 banks. It is packaged in 84-ball FBGA package.
Features
* 1.8V power supply * Double-data-rate architecture: two data transfers per clock cycle * Bi-directional, differential data strobe (DQS and /DQS) is transmitted/received with data, to be used in capturing data at the receiver * DQS is edge aligned with data for READs: centeraligned with data for WRITEs * Differential clock inputs (CK and /CK) * DLL aligns DQ and DQS transitions with CK transitions * Commands entered on each positive CK edge: data and data mask referenced to both edges of DQS * Four internal banks for concurrent operation * Data mask (DM) for write data * Burst lengths: 4, 8 * /CAS Latency (CL): 3, 4, 5 * Auto precharge operation for each burst access * Auto refresh and self refresh modes * 7.8s average periodic refresh interval * 1.8V (SSTL_18 compatible) I/O * Posted CAS by programmable additive latency for better command and data bus efficiency * Off-Chip-Driver Impedance Adjustment and On-DieTermination for better signal quality * Programmable RDQS, /RDQS output for making x 8 organization compatible to x 4 organization * /DQS, (/RDQS) can be disabled for single-ended Data Strobe operation. * FBGA package with lead free solder (Sn-Ag-Cu)
Document No. E0515E12 (Ver. 1.2) Date Published February 2006 (K) Japan URL: http://www.elpida.com Elpida Memory, Inc. 2004-2006
EDE2508AASE/16AASE-DF, -BE, -AE
Ordering Information
Part number EDE2508AASE-DF-E EDE2508AASE-BE-E EDE2508AASE-AE-E EDE2516AASE-DF-E EDE2516AASE-BE-E EDE2516AASE-AE-E Mask version A Organization (words x bits) 32M x 8 Internal Banks 4 Speed bin (CL-tRCD-tRP) DDR2-700 (5-6-6) DDR2-667 (5-5-5) DDR2-600 (5-5-5) DDR2-700 (5-6-6) DDR2-667 (5-5-5) DDR2-600 (5-5-5) Package 64-ball FBGA
16M x 16
84-ball FBGA
Part Number
E D E 25 08 A A SE - DF - E
Elpida Memory
Type D: Monolithic Device
Product Code E: DDR2
Environment code E: Lead Free
Density / Bank 25: 256Mb /4-bank Bit Organization 08: x8 16: x16 Voltage, Interface A: 1.8V, SSTL_18
Speed DF: DDR2-700 (5-6-6) BE: DDR2-667 (5-5-5) AE: DDR2-600 (5-5-5)
Package SE: FBGA (with back cover) Die Rev.
Preliminary Data Sheet E0515E12 (Ver. 1.2)
2
EDE2508AASE/16AASE-DF, -BE, -AE
Pin Configurations
/xxx indicates active low signal.
64-ball FBGA (x8 organization) 1 A NC B C D E VDD NU/ /RDQS VSS F G VDDQ H J VDDL VREF K CKE L NC M A10 N VSS P A7 R VDD A12 NC (Top view) NC NC A9 A11 A8 VSS R VDD A12 NC NC NC A3 A5 A6 A4 P A7 A9 A11 A8 VSS A1 A2 A0 VDD N VSS A3 A5 A6 A4 BA0 BA1 /CAS /CS M A10 A1 A2 A0 VDD /WE /RAS /CK ODT L NC BA0 BA1 /CAS /CS VSS VSSDL CK VDD K CKE /WE /RAS /CK ODT DQ4 DQ1 VDDQ VSSQ DQ3 VDDQ DQ2 DQ0 VSSQ VDDQ DQ5 H DQ4 J VDDL VREF VSS VSSDL CK VDD VSSQ DQ3 DQ2 VSSQ DQ5 DQ6 VSSQ DM/RDQS VSSQ /DQS VDDQ DQS VSSQ DQ7 F DQ6 G VDDQ DQ1 VDDQ VDDQ DQ0 VDDQ VSSQ LDM LDQS VSSQ DQ7 2 NC 3 7 8 NC 9 NC A VDD B DQ14 VSSQ UDM C VDDQ D E VDD NC VSS VSSQ /LDQS VDDQ DQ9 VDDQ VDDQ DQ8 VDDQ UDQS VSSQ DQ15 NC VSS VSSQ /UDQS VDDQ 1 2 84-ball FBGA (x16 organization) 3 7 8 9
DQ12 VSSQ DQ11
DQ10 VSSQ DQ13
(Top view)
Pin name A0 to A12 BA0, BA1 DQ0 to DQ15 DQS, /DQS UDQS, /UDQS LDQS, /LDQS RDQS, /RDQS /CS /RAS, /CAS, /WE CKE CK, /CK DM, UDM, LDM
Function Address inputs Bank select Data input/output Differential data strobe Differential data strobe for read Chip select Command input Clock enable Differential clock input Write data mask
Pin name ODT VDD VSS VDDQ VSSQ VREF VDDL VSSDL NC* NU*
1 2
Function ODT control Supply voltage for internal circuit Ground for internal circuit Supply voltage for DQ circuit Ground for DQ circuit Input reference voltage Supply voltage for DLL circuit Ground for DLL circuit No connection Not usable
Notes: 1. Not internally connected with die. 2. Don't use other than reserved functions.
Preliminary Data Sheet E0515E12 (Ver. 1.2)
3
EDE2508AASE/16AASE-DF, -BE, -AE
CONTENTS Description.....................................................................................................................................................1 Features.........................................................................................................................................................1 Ordering Information......................................................................................................................................2 Part Number ..................................................................................................................................................2 Pin Configurations .........................................................................................................................................3 Electrical Specifications.................................................................................................................................5 Block Diagram .............................................................................................................................................15 Pin Function.................................................................................................................................................16 Command Operation ...................................................................................................................................18 Simplified State Diagram .............................................................................................................................25 Operation of DDR2 SDRAM ........................................................................................................................26 Package Drawing ........................................................................................................................................62 Recommended Soldering Conditions..........................................................................................................64
Preliminary Data Sheet E0515E12 (Ver. 1.2)
4
EDE2508AASE/16AASE-DF, -BE, -AE
Electrical Specifications
* All voltages are referenced to VSS (GND) * Execute power-up and Initialization sequence before proper device operation is achieved. Absolute Maximum Ratings
Parameter Power supply voltage Power supply voltage for output Power supply voltage for DLL Input voltage Output voltage Storage temperature Power dissipation Short circuit output current Symbol VDD VDDQ VDDL VIN VOUT Tstg PD IOUT Rating -1.0 to +2.3 -0.5 to +2.3 -0.5 to +2.3 -0.5 to +2.3 -0.5 to +2.3 -55 to +100 1.0 50 Unit V V V V V C W mA Note 1 1 1 1 1 1, 2 1 1
Notes: 1. Stresses greater than those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. 2. Storage temperature is the case surface temperature on the center/top side of the DRAM. Caution Exposing the device to stress above those listed in Absolute Maximum Ratings could cause permanent damage. The device is not meant to be operated under conditions outside the limits described in the operational section of this specification. Exposure to Absolute Maximum Rating conditions for extended periods may affect device reliability.
Operating Temperature Condition
Parameter Operating case temperature Symbol TC Rating 0 to +85 Unit C Note 1, 2
Notes: 1. Operating temperature is the case surface temperature on the center/top side of the DRAM. 2. The operation temperature range is the temperature where all DRAM specification will be supported. Out side of this temperature range, even it is still within the limit of stress condition, some deviation on portion of operation specification may be required. During operation, the DRAM case temperature must be maintained between 0 to +85C under all other specification parameters.
Preliminary Data Sheet E0515E12 (Ver. 1.2)
5
EDE2508AASE/16AASE-DF, -BE, -AE
Recommended DC Operating Conditions (SSTL_18)
Parameter Supply voltage Supply voltage for output Supply voltage for DLL Input reference voltage Termination voltage DC input logic high DC input low AC input logic high AC input low
Symbol VDD VDDQ VDDL VREF VTT VIH (DC) VIL (DC) VIH (AC) VIL (AC)
min. 1.8 1.8 1.8 0.49 x VDDQ VREF - 0.04 VREF + 0.125 -0.3 VREF + 0.250
typ. 1.85 1.85 1.85
max. 1.9 1.9 1.9 VREF + 0.04 VDDQ + 0.3V VREF - 0.125 VREF - 0.250
Unit V V V V V V V V V
Notes 4 4 4 1, 2 3
0.50 x VDDQ 0.51 x VDDQ VREF
Notes: 1. The value of VREF may be selected by the user to provide optimum noise margin in the system. Typically the value of VREF is expected to be about 0.5 x VDDQ of the transmitting device and VREF are expected to track variations in VDDQ. 2. Peak to peak AC noise on VREF may not exceed 2% VREF (DC). 3. VTT of transmitting device must track VREF of receiving device. 4. VDDQ tracks with VDD, VDDL tracks with VDD. AC parameters are measured with VDD, VDDQ and VDDL tied together.
Preliminary Data Sheet E0515E12 (Ver. 1.2)
6
EDE2508AASE/16AASE-DF, -BE, -AE
DC Characteristics 1 (TC = 0 to +85C, VDD, VDDQ = 1.85V 0.05V)
max. Parameter Operating current (ACT-PRE) Symbol Grade -DF IDD0 -BE -AE -DF Operating current (ACT-READ-PRE) IDD1 -BE -AE -DF Precharge power-down standby current IDD2P -BE -AE -DF Precharge quiet standby IDD2Q current -BE -AE -DF Idle standby current IDD2N -BE -AE -DF IDD3P-F Active power-down standby current IDD3P-S -BE -AE -DF -BE -AE -DF Active standby current IDD3N -BE -AE -DF Operating current (Burst read operating) IDD4R -BE -AE -DF Operating current (Burst write operating) IDD4W -BE -AE x8 125 125 120 140 140 135 12 12 11 30 30 25 40 40 35 45 45 40 30 30 25 85 80 75 230 220 210 230 220 210 x 16 135 135 130 150 150 145 12 12 11 30 30 25 40 40 35 45 45 40 30 30 25 85 80 75 290 280 270 290 280 270 mA mA mA mA mA mA mA mA mA mA Unit Test condition one bank; tCK = tCK (IDD), tRC = tRC (IDD), tRAS = tRAS min.(IDD); CKE is H, /CS is H between valid commands; Address bus inputs are SWITCHING; Data bus inputs are SWITCHING one bank; IOUT = 0mA; BL = 4, CL = CL(IDD), AL = 0; tCK = tCK (IDD), tRC = tRC (IDD), tRAS = tRAS min.(IDD); tRCD = tRCD (IDD); CKE is H, /CS is H between valid commands; Address bus inputs are SWITCHING; Data pattern is same as IDD4W all banks idle; tCK = tCK (IDD); CKE is L; Other control and address bus inputs are STABLE; Data bus inputs are FLOATING all banks idle; tCK = tCK (IDD); CKE is H, /CS is H; Other control and address bus inputs are STABLE; Data bus inputs are FLOATING all banks idle; tCK = tCK (IDD); CKE is H, /CS is H; Other control and address bus inputs are SWITCHING; Data bus inputs are SWITCHING all banks open; tCK = tCK (IDD); CKE is L; Other control and address bus inputs are STABLE; Data bus inputs are FLOATING
Fast PDN Exit MRS(12) = 0
Slow PDN Exit MRS(12) = 1
all banks open; tCK = tCK (IDD), tRAS = tRAS max.(IDD), tRP = tRP (IDD); CKE is H, /CS is H between valid commands; Other control and address bus inputs are SWITCHING; Data bus inputs are SWITCHING all banks open, continuous burst reads, IOUT = 0mA; BL = 4, CL = CL(IDD), AL = 0; tCK = tCK (IDD), tRAS = tRAS max.(IDD), tRP = tRP (IDD); CKE is H, /CS is H between valid commands; Address bus inputs are SWITCHING; Data pattern is same as IDD4W all banks open, continuous burst writes; BL = 4, CL = CL(IDD), AL = 0; tCK = tCK (IDD), tRAS = tRAS max.(IDD), tRP = tRP (IDD); CKE is H, /CS is H between valid commands; Address bus inputs are SWITCHING; Data bus inputs are SWITCHING
Preliminary Data Sheet E0515E12 (Ver. 1.2)
7
EDE2508AASE/16AASE-DF, -BE, -AE
max. Parameter Symbol Grade -DF Auto-refresh current IDD5 -BE -AE x8 270 270 260 x 16 270 270 260 mA Unit Test condition tCK = tCK (IDD); Refresh command at every tRFC (IDD) interval; CKE is H, /CS is H between valid commands; Other control and address bus inputs are SWITCHING; Data bus inputs are SWITCHING Self Refresh Mode; CK and /CK at 0V; CKE 0.2V; Other control and address bus inputs are FLOATING; Data bus inputs are FLOATING all bank interleaving reads, IOUT = 0mA; BL = 4, CL = CL(IDD), AL = tRCD (IDD) -1 x tCK (IDD); tCK = tCK (IDD), tRC = tRC (IDD), tRRD = tRRD(IDD), tRCD = 1 x tCK (IDD); See Notes 7; CKE is H, CS is H between valid commands; Address bus inputs are STABLE during DESELECTs; Data pattern is same as IDD4W;
Self-refresh current
IDD6
6
6
mA
-DF Operating current (Bank interleaving) IDD7 -BE -AE
340 340 330
475 475 460 mA
Notes: 1. 2. 3. 4.
IDD specifications are tested after the device is properly initialized. Input slew rate is specified by AC Input Test Condition. IDD parameters are specified with ODT disabled. Data bus consists of DQ, DM, DQS, /DQS, RDQS, /RDQS, LDQS, /LDQS, UDQS, and /UDQS. IDD values must be met with all combinations of EMRS bits 10 and 11. 5. Definitions for IDD L is defined as VIN VIL (AC) (max.) H is defined as VIN VIH (AC) (min.) STABLE is defined as inputs stable at an H or L level FLOATING is defined as inputs at VREF = VDDQ/2 SWITCHING is defined as: inputs changing between H and L every other clock cycle (once per two clocks) for address and control signals, and inputs changing between H and L every other data transfer (once per clock) for DQ signals not including masks or strobes. 6. Refer to AC Timing for IDD Test Conditions. 7. In case of -DF (DDR2-700), tRCD must be 2 x tCK (IDD) and AL must be 4 x tCK (IDD) because AL = 5 is not supported in this device.
AC Timing for IDD Test Conditions For purposes of IDD testing, the following parameters are to be utilized.
DDR2-700 Parameter CL(IDD) tRCD(IDD) tRC(IDD) tRRD(IDD) tCK(IDD) tRAS(min.)(IDD) tRAS(max.)(IDD) tRP(IDD) tRFC(IDD) 5-6-6 5 15 67.5 7.5 2.85 50 70000 15 85 DDR2-667 5-5-5 5 15 60 7.5 3 45 70000 15 75 DDR2-600 5-5-5 5 15 65 7.5 3.3 47.5 70000 15 80 Unit tCK ns ns ns ns ns ns ns ns
Preliminary Data Sheet E0515E12 (Ver. 1.2)
8
EDE2508AASE/16AASE-DF, -BE, -AE
DC Characteristics 2 (TC = 0 to +85C, VDD, VDDQ = 1.85V 0.05V)
Parameter Input leakage current Output leakage current Symbol ILI ILO Value TBD TBD VTT + 0.603 VTT - 0.603 0.5 x VDDQ +13.4 -13.4 Unit A A V V V mA mA Notes VDD VIN VSS VDDQ VOUT VSS 5 5 1 3, 4, 5 2, 4, 5
Minimum required output pull-up under AC VOH test load Maximum required output pull-down under VOL AC test load Output timing measurement reference level VOTR Output minimum sink DC current Output minimum source DC current IOL IOH
Notes: 1. 2. 3. 4. 5.
The VDDQ of the device under test is referenced. VDDQ = 1.7V; VOUT = 1.42V. VDDQ = 1.7V; VOUT = 0.28V. The DC value of VREF applied to the receiving device is expected to be set to VTT. After OCD calibration to 18 at TC = 25C, VDD = VDDQ = 1.8V.
DC Characteristics 3 (TC = 0 to +85C, VDD, VDDQ = 1.85V 0.05V)
Parameter AC differential input voltage AC differential cross point voltage AC differential cross point voltage Symbol VID (AC) VIX (AC) VOX (AC) min. 0.5 0.5 x VDDQ - 0.175 0.5 x VDDQ - 0.125 max. VDDQ + 0.6 0.5 x VDDQ + 0.175 0.5 x VDDQ + 0.125 Unit V V V Note 1, 2 2 3
Notes: 1. VID(AC) specifies the input differential voltage |VTR - VCP| required for switching, where VTR is the true input signal (such as CK, DQS, LDQS or UDQS) and VCP is the complementary input signal (such as /CK, /DQS, /LDQS or /UDQS). The minimum value is equal to VIH(AC) - VIL(AC). 2. The typical value of VIX(AC) is expected to be about 0.5 x VDDQ of the transmitting device and VIX(AC) is expected to track variations in VDDQ . VIX(AC) indicates the voltage at which differential input signals must cross. 3. The typical value of VOX(AC) is expected to be about 0.5 x VDDQ of the transmitting device and VOX(AC) is expected to track variations in VDDQ . VOX(AC) indicates the voltage at which differential output signals must cross.
VDDQ VTR
VID
VCP VSSQ
Crossing point
VIX or VOX
Differential Signal Levels*1, 2
Preliminary Data Sheet E0515E12 (Ver. 1.2)
9
EDE2508AASE/16AASE-DF, -BE, -AE
ODT DC Electrical Characteristics (TC = 0 to +85C, VDD, VDDQ = 1.85V 0.05V)
Parameter Rtt effective impedance value for EMRS (A6, A2) = 0, 1; 75 Rtt effective impedance value for EMRS (A6, A2) = 1, 0; 150 Deviation of VM with respect to VDDQ/2 Symbol Rtt1(eff) Rtt2(eff) VM min 60 120 -3.75 typ 75 150 max 90 180 +3.75 Unit % Note 1 1 1
Note: 1. Test condition for Rtt measurements. Measurement Definition for Rtt(eff) Apply VIH (AC) and VIL (AC) to test pin separately, then measure current I(VIH(AC)) and I(VIL(AC)) respectively. VIH(AC), VIL(AC), and VDDQ values defined in SSTL_18.
Rtt(eff) =
VIH(AC) - VIL(AC) I(VIH(AC)) - I(VIL(AC))
Measurement Definition for VM Measure voltage (VM) at test pin (midpoint) with no load.
VM =
2 x VM VDDQ
- 1 x 100%
OCD Default Characteristics (TC = 0 to +85C, VDD, VDDQ = 1.85V 0.05V)
Parameter Output impedance Pull-up and pull-down mismatch Output slew rate min 12.6 0 1.5 typ 18 max 23.4 4 4.5 Unit V/ns Notes 1 1, 2 3, 4
Notes: 1. Impedance measurement condition for output source DC current: VDDQ = 1.7V; VOUT = 1420mV; (VOUT-VDDQ)/IOH must be less than 23.4 for values of VOUT between VDDQ and VDDQ-280mV. Impedance measurement condition for output sink DC current: VDDQ = 1.7V; VOUT = 280mV; VOUT/IOL must be less than 23.4 for values of VOUT between 0V and 280mV. 2. Mismatch is absolute value between pull up and pull down, both are measured at same temperature and voltage. 3. Slew rate measured from VIL(AC) to VIH(AC). 4. The absolute value of the slew rate as measured from DC to DC is equal to or greater than the slew rate as measured from AC to AC. This is guaranteed by design and characterization.
Preliminary Data Sheet E0515E12 (Ver. 1.2)
10
EDE2508AASE/16AASE-DF, -BE, -AE
Pin Capacitance (TA = 25C, VDD, VDDQ = 1.85V 0.05V)
Parameter CLK input pin capacitance Symbol CCK Pins CK /RAS, /CAS, /WE, /CS, CKE, ODT, Address DQ, DQS, /DQS, UDQS, /UDQS, LDQS, /LDQS, RDQS, /RDQS, DM, UDM, LDM min. 1.0 typ. 1.5 max. 2.0 Unit pF Notes 1
Input pin capacitance
CIN
1.0
1.5
2.0
pF
1
Input/output pin capacitance
CI/O
2.5
3.0
3.5
pF
2
Notes: 1. Matching within 0.25pF. 2. Matching within 0.50pF.
Preliminary Data Sheet E0515E12 (Ver. 1.2)
11
EDE2508AASE/16AASE-DF, -BE, -AE
AC Characteristics (TC = 0 to +85C, VDD, VDDQ = 1.85V 0.05V, VSS, VSSQ = 0V)
-DF Frequency (Mbps) Parameter /CAS latency Active to read or write command delay Precharge command period Symbol CL tRCD tRP 700 min. 5 15 15 max. 5 +450 +400 0.55 0.55 8000 tAC max. tAC max. 300 400 -BE 667 min. 5 15 15 60 -450 -400 0.45 0.45 min. (tCL, tCH) 3000 225 100 0.6 0.35 tAC min. max. 5 +450 +400 0.55 0.55 8000 tAC max. tAC max. 300 400 -AE 600 min. 5 15 15 60 -500 -450 0.45 0.45 min. (tCL, tCH) 3300 225 100 0.6 0.35 tAC min. max. 5 +500 +450 0.55 0.55 8000 tAC max. tAC max. 300 400 Unit Notes tCK ns ns ns ps ps tCK tCK ps ps ps ps tCK tCK ps ps ps ps ps tCK tCK tCK tCK tCK tCK tCK tCK tCK ps ps tCK tCK 5 4 5 4
Active to active/auto refresh tRC 60 command time DQ output access time from tAC -450 CK, /CK DQS output access time from tDQSCK -400 CK, /CK CK high-level width CK low-level width CK half period Clock cycle time DQ and DM input hold time DQ and DM input setup time Control and Address input pulse width for each input DQ and DM input pulse width for each input Data-out high-impedance time from CK,/CK Data-out low-impedance time from CK,/CK DQS-DQ skew for DQS and associated DQ signals DQ hold skew factor DQ/DQS output hold time from DQS Write command to first DQS latching transition DQS input high pulse width DQS input low pulse width tCH tCL tHP tCK tDH tDS tIPW tDIPW tHZ tLZ tDQSQ tQHS tQH tDQSS tDQSH tDQSL 0.45 0.45 min. (tCL, tCH) 2850 225 100 0.6 0.35 tAC min.
tHP - tQHS WL - 0.25 0.35 0.35 0.2 0.2 2 WL + 0.25 0.6 1.1 0.6
tHP - tQHS WL - 0.25 0.35 0.35 0.2 0.2 2 0 0.4 0.35 250 125 0.9 0.4 WL + 0.25 0.6 1.1 0.6
tHP - tQHS WL - 0.25 0.35 0.35 0.2 0.2 2 0 0.4 0.35 375 250 0.9 0.4 WL + 0.25 0.6 1.1 0.6
DQS falling edge to CK setup tDSS time DQS falling edge hold time tDSH from CK Mode register set command tMRD cycle time Write preamble setup time Write postamble Write preamble Address and control input hold time Address and control input setup time Read preamble Read postamble
tWPRES 0 tWPST tWPRE tIH tIS tRPRE tRPST 0.4 0.35 250 125 0.9 0.4
Preliminary Data Sheet E0515E12 (Ver. 1.2)
12
EDE2508AASE/16AASE-DF, -BE, -AE
-DF Frequency (Mbps) Parameter Active to auto-precharge delay Active bank A to active bank B command period Write recovery time Auto precharge write recovery + precharge time Internal write to read command delay Internal read to precharge command delay Exit self refresh to a non-read command Exit self refresh to a read command Exit precharge power down to any non-read command Exit active power down to read command Exit active power down to read command (slow exit/low power mode) CKE minimum pulse width (high and low pulse width) Output impedance test driver delay Auto refresh to active/auto refresh command time Average periodic refresh interval Minimum time clocks remains ON after CKE asynchronously drops low Symbol 700 min. 45 tRCD min. 7.5 15 max. 70000 -BE 667 min. 45 tRCD min. 7.5 15 max. 70000 -AE 600 min. 45 tRCD min. 7.5 15 max. 70000 Unit Notes ns ns ns ns tCK ns ns ns tCK tCK tCK tCK tCK ns ns s ns 3 2, 3 1
Active to precharge command tRAS tRAP tRRD tWR tDAL tWTR tRTP tXSNR tXSRD tXP tXARD
(tWR/tCK) + (tRP/tCK) 7.5 7.5 tRFC + 10 200 2 2 12 7.8
(tWR/tCK) + (tRP/tCK) 7.5 7.5 tRFC + 10 200 2 2 6 - AL 3 0 75 12 7.8
(tWR/tCK) + (tRP/tCK) 7.5 7.5 tRFC + 10 200 2 2 6 - AL 3 0 75 12 7.8
tXARDS 6 - AL tCKE tOIT tRFC tREFI tDELAY 3 0 75
tIS + tCK + tIH
tIS + tCK + tIH
tIS + tCK + tIH
Notes: 1. 2. 3. 4.
For each of the terms above, if not already an integer, round to the next higher integer. AL: Additive Latency. MRS A12 bit defines which active power down exit timing to be applied. The figures of Input Waveform Timing 1 and 2 are referenced from the input signal crossing at the VIH(AC) level for a rising signal and VIL(AC) for a falling signal applied to the device under test. 5. The figures of Input Waveform Timing 1 and 2 are referenced from the input signal crossing at the VIH(DC) level for a rising signal and VIL(DC) for a falling signal applied to the device under test.
DQS /DQS
CK /CK
tDS
tDH
tDS
tDH VDDQ VIH (AC)(min.) VIH (DC)(min.) VREF VIL (DC)(max.) VIL (AC)(max.) VSS
tIS
tIH
tIS
tIH VDDQ VIH (AC)(min.) VIH (DC)(min.) VREF VIL (DC)(max.) VIL (AC)(max.) VSS
Input Waveform Timing 1 (tDS, tDH)
Input Waveform Timing 2 (tIS, tIH)
Preliminary Data Sheet E0515E12 (Ver. 1.2)
13
EDE2508AASE/16AASE-DF, -BE, -AE
ODT AC Electrical Characteristics
Parameter ODT turn-on delay ODT turn-on ODT turn-on (power down mode) ODT turn-off delay ODT turn-off ODT turn-off (power down mode) ODT to power down entry latency ODT power down exit latency Symbol tAOND tAON tAONPD tAOFD tAOF tAOFPD tANPD tAXPD min 2 tAC(min) tAC(min) + 2000 2.5 tAC(min) tAC(min) + 2000 3 8 max 2 tAC(max) + 1000 2tCK + tAC(max) + 1000 2.5 tAC(max) + 600 2.5tCK + tAC(max) + 1000 3 8 Unit tCK ps ps tCK ps ns tCK tCK 2 1 Notes
Notes: 1. ODT turn on time min is when the device leaves high impedance and ODT resistance begins to turn on. ODT turn on time max is when the ODT resistance is fully on. Both are measured from tAOND. 2. ODT turn off time min is when the device starts to turn off ODT resistance. ODT turn off time max is when the bus is in high impedance. Both are measured from tAOFD. AC Input Test Conditions
Parameter Input reference voltage Input signal maximum peak to peak swing Input signal maximum slew rate Symbol VREF VSWING(max.) SLEW Value 0.5 x VDDQ 1.0 1.0 Unit V V V/ns Notes 1 1 2, 3
Notes: 1. Input waveform timing is referenced to the input signal crossing through the VREF level applied to the device under test. 2. The input signal minimum slew rate is to be maintained over the range from VIL(DC) (max.) to VIH(AC) (min.) for rising edges and the range from VIH(DC) (min.) to VIL(AC) (max.) for falling edges as shown in the below figure. 3. AC timings are referenced with input waveforms switching from VIL(AC) to VIH(AC) on the positive transitions and VIH(AC) to VIL(AC) on the negative transitions.
Start of falling edge input timing
Start of rising edge input timing
VDDQ VIH (AC)(min.) VIH (DC)(min.)
VSWING(max.)
VREF VIL (DC)(max.) VIL (AC)(max.)
TF Falling slew = VIH (DC)(min.) - VIL (AC)(max.) TF
TR
Rising slew =
VSS
VIH (AC) min. - VIL (DC)(max.) TR
AC Input Test Signal Wave forms
Measurement point
DQ RT =25
VTT
Output Load
Preliminary Data Sheet E0515E12 (Ver. 1.2)
14
EDE2508AASE/16AASE-DF, -BE, -AE
Block Diagram
CK /CK CKE
Clock generator
Bank 3 Bank 2 Bank 1
A0 to A12, BA0, BA1
Mode register
Row address buffer and refresh counter
Row decoder
Memory cell array Bank 0
Sense amp.
Command decoder
/CS /RAS /CAS /WE
Column address buffer and burst counter
Column decoder
Control logic
Data control circuit
Latch circuit
DQS, /DQS
CK, /CK
DLL
Input & Output buffer
RDQS, /RDQS ODT
DM
DQ
Preliminary Data Sheet E0515E12 (Ver. 1.2)
15
EDE2508AASE/16AASE-DF, -BE, -AE
Pin Function
CK, /CK (input pins) CK and /CK are differential clock inputs. All address and control input signals are sampled on the crossing of the positive edge of CK and negative edge of /CK. Output (read) data is referenced to the crossings of CK and /CK (both directions of crossing). /CS (input pin) All commands are masked when /CS is registered high. /CS provides for external rank selection on systems with multiple ranks. /CS is considered part of the command code. /RAS, /CAS, /WE (input pins) /RAS, /CAS and /WE (along with /CS) define the command being entered. A0 to A12 (input pins) Provided the row address for Active commands and the column address and Auto Precharge bit for Read/Write commands to select one location out of the memory array in the respective bank. The address inputs also provide the op-code during mode register set commands. [Address Pins Table]
Address (A0 to A12) Part number EDE2508AA EDE2516AA Row address AX0 to AX12 AX0 to AX12 Column address AY0 to AY9 AY0 to AY8
A10 (AP) (input pin) A10 is sampled during a precharge command to determine whether the precharge applies to one bank (A10 = low) or all banks (A10 = high). If only one bank is to be precharged, the bank is selected by BA0, BA1. BA0, BA1 (input pins) BA0 and BA1 define to which bank an active, read, write or precharge command is being applied. BA0 also determines if the mode register or extended mode register is to be accessed during a MRS or EMRS cycle. [Bank Select Signal Table]
BA0 Bank 0 Bank 1 Bank 2 Bank 3 L H L H BA1 L L H H
Remark: H: VIH. L: VIL. CKE (input pin) CKE high activates, and CKE low deactivates, internal clock signals and device input buffers and output drivers. Taking CKE low provides precharge power-down and Self Refresh operation (all banks idle), or active power-down (row active in any bank). CKE is synchronous for power down entry and exit, and for self refresh entry. CKE is asynchronous for self refresh exit. CKE must be maintained high throughout read and write accesses. Input buffers, excluding CK, /CK and CKE are disabled during power-down. Input buffers, excluding CKE, are disabled during selfrefresh.
Preliminary Data Sheet E0515E12 (Ver. 1.2)
16
EDE2508AASE/16AASE-DF, -BE, -AE
DM, UDM and LDM (input pins) DM is an input mask signal for write data. In 16M x 16 products, UDM and LDM control upper byte (DQ8 to DQ15) and lower byte (DQ0 to DQ7). Input data is masked when DM is sampled high coincident with that input data during a Write access. DM is sampled on both edges of DQS. Although DM pins are input only, the DM loading matches the DQ and DQS loading. For x8 configuration, DM function will be disabled when RDQS function is enabled by EMRS. DQ (input/output pins) Bi-directional data bus. DQS, /DQS, UDQS, /UDQS, LDQS, /LDQS (input/output pins) Output with read data, input with write data for source synchronous operation. In 16M x 16 products, UDQS, /UDQS and LDQS, /LDQS control upper byte (DQ8 to DQ15) and lower byte (DQ0 to DQ7). Edge-aligned with read data, centered in write data. Used to capture write data. /DQS can be disabled by EMRS. RDQS, /RDQS (output pins) Differential Data Strobe for READ operation only. DM and RDQS functions are switch able by EMRS. These pins exist only in x8 configuration. /RDQS output will be disabled when /DQS is disabled by EMRS. ODT (input pins) ODT (On Die Termination control) is a registered high signal that enables termination resistance internal to the DDR II SDRAM. When enabled, ODT is only applied to each DQ, DQS, /DQS, RDQS, /RDQS, and DM signal for x 8 configurations. For x 16 configuration, ODT is applied to each DQ, UDQS, /UDQS, LDQS, /LDQS, UDM, and LDM signal. The ODT pin will be ignored if the Extended Mode Register (EMRS) is programmed to disable ODT. VDD, VSS, VDDQ, VSSQ (power supply) VDD and VSS are power supply pins for internal circuits. VDDQ and VSSQ are power supply pins for the output buffers. VDDL and VSSDL (power supply) VDDL and VSSDL are power supply pins for DLL circuits. VREF (Power supply) SSTL_18 reference voltage: (0.50 0.01) x VDDQ
Preliminary Data Sheet E0515E12 (Ver. 1.2)
17
EDE2508AASE/16AASE-DF, -BE, -AE
Command Operation
Command Truth Table The DDR2 SDRAM recognizes the following commands specified by the /CS, /RAS, /CAS, /WE and address pins.
CKE Function Mode register set Extended mode register set Auto refresh Self refresh entry Self refresh exit Symbol MRS EMRS REF SELF SELFX Previous Current cycle cycle /CS H H H H L L Single bank precharge Precharge all banks Bank activate Write Write with auto precharge Read Read with auto precharge No operation Device deselect Power down mode entry PRE PALL ACT WRIT WRITA READ READA NOP DESL PDEN H H H H H H H H H H H Power down mode exit PDEX L L H H H L H H H H H H H H H x x L L H H L L L L H L L L L L L L L L H H L H L /RAS /CAS /WE L L L L x H L L L H H H H H x x H x H L L L L x H H H H L L L L H x x H x H L L H H x H L L H L L H H H x x H x H BA1, BA0 A12 to A11 A10 A0 to A9 Notes 1 1 1 1 1, 6
BA0 = 0 and MRS OP Code BA0 = 1 and EMRS OP Code x x x x BA x BA BA BA BA BA x x x x x x x x x x x x x x x x L H x x x x x x
1, 2 1 1, 2
Row Address Column L Column H Column L Column H x x x x x x x x x x x x
Column 1, 2, 3 Column 1, 2, 3 Column 1, 2, 3 Column 1, 2, 3 x x x x x x 1, 4 1 1 1, 4
Remark: H = VIH. L = VIL. x = VIH or VIL Notes: 1. All DDR2 commands are defined by states of /CS, /RAS, /CAS, /WE and CKE at the rising edge of the clock. 2. Bank select (BA0, BA1), determine which bank is to be operated upon. 3. Burst reads or writes should not be terminated other than specified as Reads interrupted by a Read in burst read command [READ] or Writes interrupted by a Write in burst write command [WRIT]. 4. The power down mode does not perform any refresh operations. The duration of power down is therefore limited by the refresh requirements of the device. One clock delay is required for mode entry and exit. 5. The state of ODT does not affect the states described in this table. The ODT function is not available during self-refresh. 6. Self refresh exit is asynchronous.
Preliminary Data Sheet E0515E12 (Ver. 1.2)
18
EDE2508AASE/16AASE-DF, -BE, -AE
CKE Truth Table
CKE Current state* Power down
2 *3
Previous 1 cycle (n-1)* L L
Current *1 cycle (n) L H L H L L L H
Command(n) /CS, /RAS, /CAS, /WE x DESL or NOP x DESL or NOP DESL or NOP DESL or NOP SELF
Operation (n)
*3
Notes 11, 13, 15 4, 8, 11, 13 11, 15 4, 5, 9 4, 8, 10, 11, 13 4, 8, 10, 11, 13 6, 9, 11, 13 7
Maintain power down Power down exit Maintain self refresh Self refresh exit Active power down entry Precharge power down entry Self refresh entry
Self refresh
L L
Bank Active All banks idle
H H H
Any state other than listed above
H
Refer to the Command Truth Table
Remark: H = VIH. L = VIL. x = Don't care Notes: 1. CKE (n) is the logic state of CKE at clock edge n; CKE (n-1) was the state of CKE at the previous clock edge. 2. Current state is the state of the DDR SDRAM immediately prior to clock edge n. 3. Command (n) is the command registered at clock edge n, and operation (n) is a result of Command (n). 4. All states and sequences not shown are illegal or reserved unless explicitly described elsewhere in this document. 5. On self refresh exit, [DESL] or [NOP] commands must be issued on every clock edge occurring during the tXSNR period. Read commands may be issued only after tXSRD (200 clocks) is satisfied. 6. Self refresh mode can only be entered from the all banks idle state. 7. Must be a legal command as defined in the command truth table. 8. Valid commands for power down entry and exit are [NOP] and [DESL] only. 9. Valid commands for self refresh exit are [NOP] and [DESL] only. 10. Power down and self-refresh can not be entered while read or write operations, (extended) mode register set operations or precharge operations are in progress. See section Power Down and Self Refresh Command for a detailed list of restrictions. 11. Minimum CKE high time is 3 clocks; minimum CKE low time is 3 clocks. 12. The state of ODT does not affect the states described in this table. The ODT function is not available during self-refresh. See section ODT (On Die Termination). 13. The power down does not perform any refresh operations. The duration of power down mode is therefore limited by the refresh requirements outlined in section automatic refresh command. 14. CKE must be maintained high while the SDRAM is in OCD calibration mode. 15. "x" means "don't care" (including floating around VREF) in self refresh and power down. However ODT must be driven high or low in power down if the ODT function is enabled (bit A2 or A6 set to "1" in EMRS(1) ).
Preliminary Data Sheet E0515E12 (Ver. 1.2)
19
EDE2508AASE/16AASE-DF, -BE, -AE
Function Truth Table The following tables show the operations that are performed when each command is issued in each state of the DDR SDRAM.
Current state Idle /CS H L L L L L L L L L L L L Bank(s) active H L L L L L L L L L L L L Read H L L L L L L L L L L L L /RAS /CAS /WE x H H H H H L L L L L L L x H H H H H L L L L L L L x H H H H H L L L L L L L x H L L L L H H H L L L L x H L L L L H H H L L L L x H L L L L H H H L L L L x H H H L L H L L H H L L x H H H L L H L L H H L L x H H H L L H L L H H L L Address x x
BA, CA, A10 (AP) BA, CA, A10 (AP) BA, CA, A10 (AP) BA, CA, A10 (AP) BA, RA BA, A10 (AP) A10 (AP)
Command DESL NOP READ READA WRIT WRITA ACT PRE PALL REF SELF MRS EMRS DESL NOP READ READA WRIT WRITA ACT PRE PALL REF SELF MRS EMRS DESL NOP READ READA WRIT WRITA ACT PRE PALL REF SELF MRS EMRS
Operation Nop or Power down Nop or Power down ILLEGAL ILLEGAL ILLEGAL ILLEGAL Row activating Precharge Precharge all banks Auto refresh Self refresh Mode register accessing Extended mode register accessing Nop Nop Begin Read Begin Read Begin Write Begin Write ILLEGAL Precharge Precharge all banks ILLEGAL ILLEGAL ILLEGAL ILLEGAL Continue burst to end -> Row active Continue burst to end -> Row active Burst interrupt Burst interrupt ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL
Notes
1 1 1 1
x x
BA, MRS-OPCODE BA, EMRS-OPCODE
2 2 2 2
x x
BA, CA, A10 (AP) BA, CA, A10 (AP) BA, CA, A10 (AP) BA, CA, A10 (AP) BA, RA BA, A10 (AP) A10 (AP)
1
x x
BA, MRS-OPCODE BA, EMRS-OPCODE
x x
BA, CA, A10 (AP) BA, CA, A10 (AP) BA, CA, A10 (AP) BA, CA, A10 (AP) BA, RA BA, A10 (AP) A10 (AP)
1, 4 1, 4 1 1 1 1
x x
BA, MRS-OPCODE BA, EMRS-OPCODE
Preliminary Data Sheet E0515E12 (Ver. 1.2)
20
EDE2508AASE/16AASE-DF, -BE, -AE
Current state Write /CS H L L L L L L L L L L L L Read with auto precharge H L L L L L L L L L L L L Write with auto Precharge H L L L L L L L L L L L L /RAS /CAS /WE x H H H H H L L L L L L L x H H H H H L L L L L L L x H H H H H L L L L L L L x H L L L L H H H L L L L x H L L L L H H H L L L L x H L L L L H H H L L L L x H H H L L H L L H H L L x H H H L L H L L H H L L x H H H L L H L L H H L L Address x x
BA, CA, A10 (AP) BA, CA, A10 (AP) BA, CA, A10 (AP) BA, CA, A10 (AP) BA, RA BA, A10 (AP) A10 (AP)
Command DESL NOP READ READA WRIT WRITA ACT PRE PALL REF SELF MRS
Operation Continue burst to end -> Write recovering Continue burst to end -> Write recovering ILLEGAL ILLEGAL Burst interrupt Burst interrupt ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL Continue burst to end -> Precharging Continue burst to end -> Precharging ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL Continue burst to end ->Write recovering with auto precharge Continue burst to end ->Write recovering with auto precharge ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL
Note
1 1 1, 4 1, 4 1 1
x x
BA, MRS-OPCODE
BA, EMRS-OPCODE EMRS
x x
BA, CA, A10 (AP) BA, CA, A10 (AP) BA, CA, A10 (AP) BA, CA, A10 (AP) BA, RA BA, A10 (AP) A10 (AP)
DESL NOP READ READA WRIT WRITA ACT PRE PALL REF SELF MRS
1 1 1 1 1 1
x x
BA, MRS-OPCODE
BA, EMRS-OPCODE EMRS
x x
BA, CA, A10 (AP) BA, CA, A10 (AP) BA, CA, A10 (AP) BA, CA, A10 (AP) BA, RA BA, A10 (AP) A10 (AP)
DESL NOP READ READA WRIT WRITA ACT PRE PALL REF SELF MRS
1 1 1 1 1 1
x x
BA, MRS-OPCODE
BA, EMRS-OPCODE EMRS
Preliminary Data Sheet E0515E12 (Ver. 1.2)
21
EDE2508AASE/16AASE-DF, -BE, -AE
Current state Precharging
/CS H L L L L L L L L L L L L
/RAS /CAS /WE x H H H H H L L L L L L L x H H H H H L L L L L L L x H H H H H L L L L L L L x H L L L L H H H L L L L x H L L L L H H H L L L L x H L L L L H H H L L L L x H H H L L H L L H H L L x H H H L L H L L H H L L x H H H L L H L L H H L L
Address x x
BA, CA, A10 (AP) BA, CA, A10 (AP) BA, CA, A10 (AP) BA, CA, A10 (AP) BA, RA BA, A10 (AP) A10 (AP)
Command DESL NOP READ READA WRIT WRITA ACT PRE PALL REF SELF MRS EMRS DESL NOP READ READA WRIT WRITA ACT PRE PALL REF SELF MRS EMRS DESL NOP READ READA WRIT WRITA ACT PRE PALL REF SELF MRS EMRS
Operation Nop -> Enter idle after tRP Nop -> Enter idle after tRP ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL Nop -> Enter idle after tRP Nop -> Enter idle after tRP ILLEGAL ILLEGAL ILLEGAL ILLEGAL Nop -> Enter bank active after tRCD Nop -> Enter bank active after tRCD ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL Nop -> Enter bank active after tWR Nop -> Enter bank active after tWR ILLEGAL ILLEGAL New write New write ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL
Note
1 1 1 1 1
x x
BA, MRS-OPCODE BA, EMRS-OPCODE
Row activating
H L L L L L L L L L L L L
x x
BA, CA, A10 (AP) BA, CA, A10 (AP) BA, CA, A10 (AP) BA, CA, A10 (AP) BA, RA BA, A10 (AP) A10 (AP)
1 1 1 1 1
x x
BA, MRS-OPCODE BA, EMRS-OPCODE
Write recovering
H L L L L L L L L L L L L
x x
BA, CA, A10 (AP) BA, CA, A10 (AP) BA, CA, A10 (AP) BA, CA, A10 (AP) BA, RA BA, A10 (AP) A10 (AP)
1 1
1 1
x x
BA, MRS-OPCODE BA, EMRS-OPCODE
Preliminary Data Sheet E0515E12 (Ver. 1.2)
22
EDE2508AASE/16AASE-DF, -BE, -AE
Current state Write recovering with auto precharge
/CS H L L L L L L L L L L L L
/RAS /CAS /WE x H H H H H L L L L L L L x H H H H H L L L L L L L x H H H H H L L L L L L L x H L L L L H H H L L L L x H L L L L H H H L L L L x H L L L L H H H L L L L x H H H L L H L L H H L L x H H H L L H L L H H L L x H H H L L H L L H H L L
Address x x
BA, CA, A10 (AP) BA, CA, A10 (AP) BA, CA, A10 (AP) BA, CA, A10 (AP) BA, RA BA, A10 (AP) A10 (AP)
Command DESL NOP READ READA WRIT WRITA ACT PRE PALL REF SELF MRS EMRS DESL NOP READ READA WRIT WRITA ACT PRE PALL REF SELF MRS EMRS DESL NOP READ READA WRIT WRITA ACT PRE PALL REF SELF MRS EMRS
Operation Nop -> Enter bank active after tWR Nop -> Enter bank active after tWR ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL Nop -> Enter idle after tRFC Nop -> Enter idle after tRFC ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL Nop -> Enter idle after tMRD Nop -> Enter idle after tMRD ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL
Note
1 1 1 1 1 1
x x
BA, MRS-OPCODE BA, EMRS-OPCODE
Refresh
H L L L L L L L L L L L L
x x
BA, CA, A10 (AP) BA, CA, A10 (AP) BA, CA, A10 (AP) BA, CA, A10 (AP) BA, RA BA, A10 (AP) A10 (AP)
x x
BA, MRS-OPCODE BA, EMRS-OPCODE
Mode register accessing
H L L L L L L L L L L L L
x x
BA, CA, A10 (AP) BA, CA, A10 (AP) BA, CA, A10 (AP) BA, CA, A10 (AP) BA, RA BA, A10 (AP) A10 (AP)
x x
BA, MRS-OPCODE BA, EMRS-OPCODE
Preliminary Data Sheet E0515E12 (Ver. 1.2)
23
EDE2508AASE/16AASE-DF, -BE, -AE
Current state Extended Mode
/CS H
/RAS /CAS /WE x H H H H H L L L L L L L x H L L L L H H H L L L L x H H H L L H L L H H L L
Address x x
BA, CA, A10 (AP) BA, CA, A10 (AP) BA, CA, A10 (AP) BA, CA, A10 (AP) BA, RA BA, A10 (AP) A10 (AP)
Command DESL NOP READ READA WRIT WRITA ACT PRE PALL REF SELF MRS EMRS
Operation Nop -> Enter idle after tMRD Nop -> Enter idle after tMRD ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL
Note
register accessing L L L L L L L L L L L L
x x
BA, MRS-OPCODE BA, EMRS-OPCODE
Remark: Notes: 1. 2. 3. 4.
H = VIH. L = VIL. x = VIH or VIL This command may be issued for other banks, depending on the state of the banks. All banks must be in "IDLE". All AC timing specs must be met. Only allowed at the boundary of 4 bits burst. Burst interruption at other timings are illegal.
Preliminary Data Sheet E0515E12 (Ver. 1.2)
24
EDE2508AASE/16AASE-DF, -BE, -AE
Simplified State Diagram
CKEL
INITALIZATION
AUTO REFRESH
SELF REFRESH
SE
tRFC
REF
LF
X
CKEL
SE
LF
PRECHARGE POWER DOWN
PDEN CKEH
IDLE
MRS tMRD
MRS EMRS
ACT
ACTIVATING
WL + BL/2 + tWR
tRCD
PRE
tRP
RL + tRTP
WRITA
PRECHARGE
READA
WRITA
WRIT
PR
E
REA
DA
READA
READ
PR E
WRITE
READ
W RI
READ
W
PRE
RE AD
RI
TA
T
A
CKEL ACTIVE POWER DOWN PDEN
RE
AD
BANK ACTIVE CKEH
Automatic sequence Command sequence
Simplified State Diagram
Preliminary Data Sheet E0515E12 (Ver. 1.2)
25
EDE2508AASE/16AASE-DF, -BE, -AE
Operation of DDR2 SDRAM
Read and write accesses to the DDR2 SDRAM are burst oriented; accesses start at a selected location and continue for the fixed burst length of four or eight in a programmed sequence. Accesses begin with the registration of an active command, which is then followed by a read or write command. The address bits registered coincident with the active command is used to select the bank and row to be accessed (BA0, BA1 select the bank; A0 to A12 select the row). The address bits registered coincident with the read or write command are used to select the starting column location for the burst access and to determine if the auto precharge command is to be issued. Prior to normal operation, the DDR2 SDRAM must be initialized. The following sections provide detailed information covering device initialization; register definition, command descriptions and device operation. Power On and Initialization DDR2 SDRAMs must be powered up and initialized in a predefined manner. Operational procedures other than those specified may result in undefined operation. Power-Up and Initialization Sequence The following sequence is required for power up and initialization. 1 1. Apply power and attempt to maintain CKE below 0.2 x VDDQ and ODT * at a low state (all other inputs may be undefined.) VDD, VDDL and VDDQ are driven from a single power converter output, AND VTT is limited to 0.95V max, AND VREF tracks VDDQ/2. or Apply VDD before or at the same time as VDDL. Apply VDDL before or at the same time as VDDQ. Apply VDDQ before or at the same time as VTT and VREF. at least one of these two sets of conditions must be met. 2. Start clock and maintain stable condition. 3. For the minimum of 200s after stable power and clock(CK, /CK), then apply [NOP] or [DESL] and take CKE high. 4. Wait minimum of 400ns then issue precharge all command. [NOP] or [DESL] applied during 400ns period. 5. Issue EMRS(2) command. (To issue EMRS(2) command, provide low to BA0, high to BA1.) 6. Issue EMRS(3) command. (To issue EMRS(3) command, high to BA0 and BA1.) 7. Issue EMRS to enable DLL. (To issue DLL enable command, provide low to A0, high to BA0 and low to BA1.) 8. Issue a mode register set command for DLL reset. (To issue DLL reset command, provide high to A8 and low to BA0, BA1.) 9. Issue precharge all command. 10. Issue 2 or more auto-refresh commands. 11. Issue a mode register set command with low to A8 to initialize device operation. (i.e. to program operating parameters without resetting the DLL.) 12. At least 200 clocks after step 8, execute OCD calibration (Off Chip Driver impedance adjustment). If OCD calibration is not used, EMRS OCD default command (A9 = A8 = A7 = 1) followed by EMRS OCD calibration mode exit command (A9 = A8 = A7 = 0) must be issued with other operating parameters of EMRS. 13. The DDR2 SDRAM is now ready for normal operation. Note: 1. To guarantee ODT off, VREF must be valid and a low level must be applied to the ODT pin.
tCH tCL
CK /CK
tIS
CKE
Command
NOP
PALL
tRP
EMRS
tMRD
MRS
tMRD
PALL
tRP
REF
tRFC
REF
tRFC
MRS
tMRD
EMRS
Follow OCD Flowchart
EMRS
tOIT
Any command
400ns
DLL enable
DLL reset
OCD default
OCD calibration mode exit
200 cycles (min)
Power up and Initialization Sequence
Preliminary Data Sheet E0515E12 (Ver. 1.2)
26
EDE2508AASE/16AASE-DF, -BE, -AE
Programming the Mode Register and Extended Mode Registers For application flexibility, burst length, burst type, /CAS latency, DLL reset function, write recovery time(tWR) are user defined variables and must be programmed with a mode register set command [MRS]. Additionally, DLL disable function, driver impedance, additive /CAS latency, ODT(On Die Termination), single-ended strobe, and OCD (Off-Chip Driver Impedance Adjustment) are also user defined variables and must be programmed with an extended mode register set command [EMRS]. Contents of the Mode Register (MR) or Extended Mode Registers (EMR(#)) can be altered by reexecuting the MRS and EMRS commands. If the user chooses to modify only a subset of the MRS or EMRS variables, all variables must be redefined when the MRS or EMRS commands are issued. MRS, EMRS and Reset DLL do not affect array contents, which means reinitialization including those can be executed any time after power-up without affecting array contents.
DDR2 SDRAM Mode Register Set [MRS] The mode register stores the data for controlling the various operating modes of DDR2 SDRAM. It controls /CAS latency, burst length, burst sequence, test mode, DLL reset, tWR and various vendor specific options to make DDR2 SDRAM useful for various applications. The default value of the mode register is not defined, therefore the mode register must be written after power-up for proper operation. The mode register is written by asserting low on /CS, /RAS, /CAS, /WE, BA0 and BA1, while controlling the state of address pins A0 to A12. The DDR2 SDRAM should be in all bank precharge with CKE already high prior to writing into the mode register. The mode register set command cycle time (tMRD) is required to complete the write operation to the mode register. The mode register contents can be changed using the same command and clock cycle requirements during normal operation as long as all banks are in the precharge state. The mode register is divided into various fields depending on functionality. Burst length is defined by A0 to A2 with options of 4 and 8 bit burst lengths. The burst length decodes are compatible with DDR SDRAM. Burst address sequence type is defined by A3, /CAS latency is defined by A4 to A6. The DDR2 doesn't support half clock latency mode. A7 is used for test mode. A8 is used for DLL reset. A7 must be set to low for normal MRS operation. Write recovery time tWR is defined by A9 to A11. Refer to the table for specific codes.
BA1 BA0 A12 A11 A10 A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
Address field
0*1
0
PD
WR
DLL TM
/CAS latency
BT
Burst length
Mode register
A8 0 1
BA1 BA0 0 0 1 1
0 1 0 1
DLL reset No Yes
A7 0 1
Mode Normal Test
A3 0 1
Burst type Sequential Interleave
Burst length A2 0 0 A1 1 1 A0 0 1 BL 4 8
MRS mode MRS EMRS(1) EMRS(2): Reserved EMRS(3): Reserved
Write recovery for autoprecharge A11 0 0 0 0 1 1 1 1 A10 0 0 1 1 0 0 1 1 A9 0 1 0 1 0 1 0 1 WR Reserved
DDR400 DDR533
DDR667
/CAS latency A6 0 0
DDR800
A5 0 0 1 1 0 0 1 1
A4 0 1 0 1 0 1 0 1
Latency Reserved Reserved Reserved 3 4 5 Reserved Reserved
2 3 4 5 6 Reserved Reserved
0 0 1 1 1 1
A12 0 1
Active power down exit timing Fast exit (use tXARD timing) Slow exit (use tXARDS timing)
Notes: 1. BA1 is reserved for future use and must be programmed to 0 when setting the mode register. 2. WR (min.) (Write Recovery for autoprecharge) is determined by tCK (max.) and WR (max.) is determined by tCK (min.). WR in clock cycles is calculated by dividing tWR (in ns) by tCK (in ns) and rounding up to the next integer (WR [cycles] = tWR (ns) / tCK (ns)). The mode register must be programmed to this value. This is also used with tRP to determine tDAL.
Mode Register Set (MRS)
Preliminary Data Sheet E0515E12 (Ver. 1.2)
27
EDE2508AASE/16AASE-DF, -BE, -AE
DDR2 SDRAM Extended Mode Registers Set [EMRS] EMRS(1) Programming The extended mode register(1) stores the data for enabling or disabling the DLL, output driver strength, additive latency, ODT, /DQS disable, OCD program, RDQS enable. The default value of the extended mode register(1) is not defined, therefore the extended mode register(1) must be written after power-up for proper operation. The extended mode register(1) is written by asserting low on /CS, /RAS, /CAS, /WE, high on BA0 and low on BA1, while controlling the states of address pins A0 to A12. The DDR2 SDRAM should be in all bank precharge with CKE already high prior to writing into the extended mode register(1). The mode register set command cycle time (tMRD) must be satisfied to complete the write operation to the extended mode register(1). Mode register contents can be changed using the same command and clock cycle requirements during normal operation as long as all banks are in the precharge state. A0 is used for DLL enable or disable. A1 is used for enabling a half strength output driver. A3 to A5 determines the additive latency, A7 to A9 are used for OCD control, A10 is used for /DQS disable and A11 is used for RDQS enable. A2 and A6 are used for ODT setting.
BA1 BA0 A12 A11 A10 A9
A8
A7
A6
A5
A4
A3
A2
A1
A0 Address field
0
1
Qoff RDQS /DQS OCD program
Rtt Additive latency Rtt D.I.C DLL
Extended mode register
BA1 BA0 0 0 0 1 1
1 0 1
MRS mode MRS EMRS(1) EMRS(2): Reserved EMRS(3): Reserved
A6 0 0 1 1 A2 0 1 0 1
Rtt (nominal ) ODT Disabled 75 150 Reserved
A0 0 1
DLL enable Enable Disable
Driver impedance adjustment A9 0 0 0 1 1
A12 0 1 Qoff Output buffers enabled Output buffers disabled
A8 0 0 1 0 1
A7 0 1 0 0 1 Drive(1) Drive(0)
Operation
OCD calibration mode exit
Additive latency A5 0 0 0 0 1 1 1 1 A4 0 0 1 1 0 0 1 1 A3 0 1 0 1 0 1 0 1 Latency 0 1 2 3 4 Reserved Reserved Reserved
Adjust mode* 1 OCD Calibration default* 2
A10 0 1
/DQS enable Enable Disable
Driver strength control Output driver Driver size 100% 60% A1 0 1
A11 (RDQS enable) 0 0 1 1 A10 0 (Enable) 1 (Disable) 0 (Enable) 1 ( Disable) DM DM RDQS RDQS
A11 0 1
RDQS enable Disable Enable
impedance control Normal Weak
Strobe function matrix
(/DQS enable) RDQS/DM
/RDQS High-Z High-Z /RDQS High-Z
DQS DQS DQS DQS DQS
/DQS /DQS High-Z /DQS High-Z
Notes: 1. When adjust mode is issued, AL from previously set value must be applied. 2. After setting to default, OCD mode needs to be exited by setting A9 to A7 to 000. Refer to the chapter Off-Chip Driver (OCD)Impedance Adjustment for detailed information.
EMRS(1)
Preliminary Data Sheet E0515E12 (Ver. 1.2)
28
EDE2508AASE/16AASE-DF, -BE, -AE
DLL Enable/Disable The DLL must be enabled for normal operation. DLL enable is required during power up initialization, and upon returning to normal operation after having the DLL disabled. The DLL is automatically disabled when entering selfrefresh operation and is automatically re-enabled upon exit of self-refresh operation. Any time the DLL is enabled (and subsequently reset), 200 clock cycles must occur before a read command can be issued to allow time for the internal clock to be synchronized with the external clock. Failing to wait for synchronization to occur may result in a violation of the tAC or tDQSCK parameters. EMRS(2) Programming: Reserved*1
BA1 BA0 A12 A11 A10 A9 A8 0*1 A7 A6 A5 A4 A3 A2 A1 A0
Address field Extended mode register (2)
1
0
Note : 1. EMRS(2) is reserved for future use and all bits except BA0 and BA1 must be programmed to 0 when setting the mode register during initialization.
EMRS(2)
EMRS(3) Programming: Reserved*1
BA1 BA0 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0
Address Field Extended Mode Register(3)
1
1
0*1
Note : 1. EMRS (3) is reserved for future use and all bits except BA0 and BA1 must be programmed to 0 when setting the mode register during initialization.
EMRS(3)
Preliminary Data Sheet E0515E12 (Ver. 1.2)
29
EDE2508AASE/16AASE-DF, -BE, -AE
Off-Chip Driver (OCD) Impedance Adjustment DDR2 SDRAM supports driver calibration feature and the OCD Flow Chart is an example of sequence. Every calibration mode command should be followed by "OCD calibration mode exit" before any other command being issued. MRS should be set before entering OCD impedance adjustment and ODT (On Die Termination) should be carefully controlled depending on system environment.
MRS should be set before entering OCD impedance adjustment and ODT should be carefully controlled depending on system environment Start EMRS: OCD calibration mode exit
EMRS: Drive(1) DQ & DQS high ; /DQS low
EMRS: Drive(0) DQ & DQS low ; /DQS high
ALL OK Test Need calibration EMRS: OCD calibration mode exit
ALL OK
Test Need calibration
EMRS: OCD calibration mode exit
EMRS : Enter Adjust Mode
EMRS : Enter Adjust Mode
BL=4 code input to all DQs Inc, Dec, or NOP
BL=4 code input to all DQs Inc, Dec, or NOP
EMRS: OCD calibration mode exit
EMRS: OCD calibration mode exit
EMRS: OCD calibration mode exit
End
OCD Flow Chart
Preliminary Data Sheet E0515E12 (Ver. 1.2)
30
EDE2508AASE/16AASE-DF, -BE, -AE
Extended Mode Register Set for OCD Impedance Adjustment OCD impedance adjustment can be done using the following EMRS mode. In drive mode all outputs are driven out by DDR2 SDRAM and drive of RDQS is dependent on EMRS bit enabling RDQS operation. In Drive(1) mode, all DQ, DQS (and RDQS) signals are driven high and all /DQS signals are driven low. In drive(0) mode, all DQ, DQS (and RDQS) signals are driven low and all /DQS signals are driven high. In adjust mode, BL = 4 of operation code data must be used. In case of OCD calibration default, output driver characteristics follow approximate nominal V/I curve for 18 output drivers, but are not guaranteed. If tighter control is required, which is controlled within 18 3 driver impedance range, OCD must be used. [OCD Mode Set Program]
A9 0 0 0 1 1 A8 0 0 1 0 1 A7 0 1 0 0 1 Operation OCD calibration mode exit Drive (1) DQ, DQS, (RDQS) high and /DQS low Drive (0) DQ, DQS, (RDQS) low and /DQS high Adjust mode OCD calibration default
OCD Impedance Adjustment To adjust output driver impedance, controllers must issue the ADJUST EMRS command along with a 4bit burst code to DDR2 SDRAM as in OCD Adjustment Program table. For this operation, burst length has to be set to BL = 4 via MRS command before activating OCD and controllers must drive this burst code to all DQs at the same time. DT0 in OCD Adjustment Program table means all DQ bits at bit time 0, DT1 at bit time 1, and so forth. The driver output impedance is adjusted for all DDR2 SDRAM DQs simultaneously and after OCD calibration, all DQs of a given DDR2 SDRAM will be adjusted to the same driver strength setting. The maximum step count for adjustment is 16 and when the limit is reached, further increment or decrement code has no effect. The default setting may be any step within the 16-step range. [OCD Adjustment Program]
4bits burst data inputs to all DQs DT0 0 0 0 0 1 0 0 1 1 DT1 0 0 0 1 0 1 1 0 0 DT2 0 0 1 0 0 0 1 0 1 DT3 0 1 0 0 0 1 0 1 0 Operation Pull-up driver strength NOP Increase by 1 step Decrease by 1 step NOP NOP Increase by 1 step Decrease by 1 step Increase by 1 step Decrease by 1 step Reserved Pull-down driver strength NOP NOP NOP Increase by 1 step Decrease by 1 step Increase by 1 step Increase by 1 step Decrease by 1 step Decrease by 1 step
Other combinations
Preliminary Data Sheet E0515E12 (Ver. 1.2)
31
EDE2508AASE/16AASE-DF, -BE, -AE
For proper operation of adjust mode, WL = RL - 1 = AL + CL - 1 clocks and tDS/tDH should be met as the Output Impedance Control Register Set Cycle. For input data pattern for adjustment, DT0 to DT3 is a fixed order and not affected by MRS addressing mode (i.e. sequential or interleave).
/CK CK
Command
EMRS
WL
NOP
tWR
EMRS
NOP
DQS, /DQS
tDS tDH
DQ_in
DT0 OCD adjust mode
DT1
DT2
DT3 OCD calibration mode exit
Output Impedance Control Register Set Cycle
Drive Mode Drive mode, both drive (1) and drive (0), is used for controllers to measure DDR2 SDRAM Driver impedance before OCD impedance adjustment. In this mode, all outputs are driven out tOIT after "Enter drive mode" command and all output drivers are turned-off tOIT after "OCD calibration mode exit" command as the "Output Impedance Measurement/Verify Cycle".
/CK CK
Command
EMRS
NOP
EMRS
High-Z DQS, /DQS
DQs high and /DQS low for drive (1), DQs low and /DQS high for drive (0)
High-Z
DQs high for drive (1) DQ tOIT DQs low for drive (0)
tOIT
Enter drivemode
OCD Calibration mode exit
Output Impedance Measurement/Verify Cycle
Preliminary Data Sheet E0515E12 (Ver. 1.2)
32
EDE2508AASE/16AASE-DF, -BE, -AE
ODT (On Die Termination) On Die Termination (ODT), is a feature that allows a DRAM to turn on/off termination resistance for each DQ, DQS, /DQS, RDQS, /RDQS, and DM signal for x 8 configuration via the ODT control pin. For x 16 configuration ODT is applied to each DQ, UDQS, /UDQS, LDQS, /LDQS, UDM, and LDM signal via the ODT control pin. The ODT feature is designed to improve signal integrity of the memory channel by allowing the DRAM controller to independently turn on/off termination resistance for any or all DRAM devices. The ODT function is turned off and not supported in self-refresh mode.
VDDQ
VDDQ
sw1
sw2
Rval1 DRAM input buffer Rval1
Rval2 Input Pin Rval2
sw1
sw2
VSSQ
VSSQ
Switch sw1 or sw2 is enabled by ODT pin. Selection between sw1 or sw2 is determined by Rtt (nominal) in EMRS Termination included on all DQs, DM, DQS, /DQS, RDQS and /RDQS pins. Target Rtt ( ) = (Rval1) / 2 or (Rval2) / 2
Functional Representation of ODT
Preliminary Data Sheet E0515E12 (Ver. 1.2)
33
EDE2508AASE/16AASE-DF, -BE, -AE
/CK CK
T0
T1
T2
T3
T4
T5
T6
CKE
tAXPD 6tCK
tIS
tIS
ODT
tAOND
tAOFD
Internal Term Res.
tAON min.
Rtt
tAOF min. tAON max. tAOF max.
ODT Timing for Active and Standby Mode
/CK CK
T0
T1
T2
T3
T4
T5
T6
CKE
tAXPD 6tCK
tIS
tIS
ODT
tAOFPD max.
tAOFPD min.
Internal Term Res.
tAONPD min.
tAONPD max.
Rtt
ODT Timing for Power down Mode
Preliminary Data Sheet E0515E12 (Ver. 1.2)
34
EDE2508AASE/16AASE-DF, -BE, -AE
T-5 /CK CK tANPD tIS CKE T-4 T-3 T-2 T-1 T0 T1 T2 T3 T4
Entering slow exit active power down mode or precharge power down mode.
tIS ODT tAOFD Internal Term Res. Rtt tIS ODT tAOFPD(max.) Internal Term Res. tIS ODT tAOND Internal Term Res. tIS ODT tAONPD(max.) Internal Term Res. Rtt Rtt Rtt
Active and standby mode timings to be applied.
Power down mode timings to be applied.
Active and standby mode timings to be applied.
Power down mode timings to be applied.
ODT Timing Mode Switch at Entering Power Down Mode
Preliminary Data Sheet E0515E12 (Ver. 1.2)
35
EDE2508AASE/16AASE-DF, -BE, -AE
T0 /CK CK tIS CKE
tAXPD
T1
T4
T5
T6
T7
T8
T9
T10
T11
Exiting from slow active power down mode or precharge power down mode.
tIS
Active and standby mode timings to be applied.
ODT
tAOFD
Internal Term Res. tIS
Rtt
Power down mode timings to be applied.
ODT
tAOFPD (max.)
Internal Term Res.
Rtt
tIS
Active and standby mode timings to be applied.
ODT
tAOND
Internal Term Res. tIS
Rtt
Power down mode timings to be applied.
ODT
tAONPD(max.)
Internal Term Res.
Rtt
ODT Timing Mode Switch at Exiting Power Down Mode
Preliminary Data Sheet E0515E12 (Ver. 1.2)
36
EDE2508AASE/16AASE-DF, -BE, -AE
Bank Activate Command [ACT] The bank activate command is issued by holding /CAS and /WE high with /CS and /RAS low at the rising edge of the clock. The bank addresses BA0 and BA1, are used to select the desired bank. The row address A0 through A12 is used to determine which row to activate in the selected bank. The Bank activate command must be applied before any read or write operation can be executed. Immediately after the bank active command, the DDR2 SDRAM can accept a read or write command on the following clock cycle. If a R/W command is issued to a bank that has not satisfied the tRCD (min.) specification, then additive latency must be programmed into the device to delay when the R/W command is internally issued to the device. The additive latency value must be chosen to assure tRCD (min.) is satisfied. Additive latencies of 0, 1, 2, 3 and 4 are supported. Once a bank has been activated it must be precharged before another bank activate command can be applied to the same bank. The bank active and precharge times are defined as tRAS and tRP, respectively. The minimum time interval between successive bank activate commands to the same bank is determined by the /RAS cycle time of the device (tRC), which is equal to tRAS + tRP. The minimum time interval between successive bank activate commands to the different bank is determined by (tRRD).
/CK CK Command
T0
T1
T2
T3
Tn
Tn+1
Tn+2
Tn+3
ACT
Posted READ
ACT
Posted READ
PRE
PRE
ACT
tRCD(min.)
Address
ROW: 0
COL: 0
ROW: 1
tCCD
COL: 1
ROW: 0
tRCD =1
tRRD
Additive latency (AL)
Bank0 Read begins
tRAS tRC
tRP
Bank0 Active
Bank1 Active
Bank0 Precharge
Bank1 Precharge
Bank0 Active
Bank Activate Command Cycle (tRCD = 3, AL = 2, tRP = 3, tRRD = 2, tCCD = 2)
Preliminary Data Sheet E0515E12 (Ver. 1.2)
37
EDE2508AASE/16AASE-DF, -BE, -AE
Read and Write Access Modes After a bank has been activated, a read or write cycle can be executed. This is accomplished by setting /RAS high, /CS and /CAS low at the clock's rising edge. /WE must also be defined at this time to determine whether the access cycle is a read operation (/WE high) or a write operation (/WE low). The DDR2 SDRAM provides a fast column access operation. A single read or write command will initiate a serial read or write operation on successive clock cycles. The boundary of the burst cycle is strictly restricted to specific segments of the page length. For example, the 32M bits x 4 I/O x 4 banks chip has a page length of 2048 bits (defined by CA0 to CA9, CA11). The page length of 2048 is divided into 512 uniquely addressable boundary segments (4 bits each). A 4 bits burst operation will occur entirely within one of the 512 groups beginning with the column address supplied to the device during the read or write command (CA0 to CA9, CA11). The second, third and fourth access will also occur within this group segment, however, the burst order is a function of the starting address, and the burst sequence. A new burst access must not interrupt the previous 4-bit burst operation. The minimum /CAS to /CAS delay is defined by tCCD, and is a minimum of 2 clocks for read or write cycles. Posted /CAS Posted /CAS operation is supported to make command and data bus efficient for sustainable bandwidths in DDR2 SDRAM. In this operation, the DDR2 SDRAM allows a /CAS read or write command to be issued immediately after the /RAS bank activate command (or any time during the /RAS-/CAS-delay time, tRCD, period). The command is held for the time of the Additive Latency (AL) before it is issued inside the device. The Read Latency (RL) is controlled by the sum of AL and the /CAS latency (CL). Therefore if a user chooses to issue a R/W command before the tRCD (min), then AL (greater than 0) must be written into the EMRS. The Write Latency (WL) is always defined as RL - 1 (read latency -1) where read latency is defined as the sum of additive latency plus /CAS latency (RL = AL + CL).
-1 /CK CK Command
ACT READ
NOP
WRIT NOP WL = RL n-1 = 4
0
1
2
3
4
5
6
7
8
9
10
11
12
AL = 2 DQS, /DQS > = tRCD
CL = 3
RL = AL + CL = 5
DQ > = tRAC
out0 out1 out2 out3
in0 in1 in2 in3
Read Followed by a Write to the Same Bank [AL = 2 and CL = 3, RL = (AL + CL) = 5, WL = (RL - 1) = 4]
-1
/CK CK Command
0
1
2
3
4
5
6
7
8
9
10
11
12
ACT
NOP
AL = 0 READ
NOP
WRIT WL = RL n-1 = 2
NOP
CL = 3 DQS, /DQS > = tRCD DQ > = tRAC RL = AL + CL = 3
out0 out1 out2 out3
in0 in1 in2 in3
Read Followed by a Write to the Same Bank [AL = 0 and CL = 3, RL = (AL + CL) = 3, WL = (RL - 1) = 2]
Preliminary Data Sheet E0515E12 (Ver. 1.2)
38
EDE2508AASE/16AASE-DF, -BE, -AE
Burst Mode Operation Burst mode operation is used to provide a constant flow of data to memory locations (write cycle), or from memory locations (read cycle). The parameters that define how the burst mode will operate are burst sequence and burst length. DDR2 SDRAM supports 4 bits burst and 8bits burst modes only. For 8 bits burst mode, full interleave address ordering is supported, however, sequential address ordering is nibble based for ease of implementation. The burst type, either sequential or interleaved, is programmable and defined by the address bit 3 (A3) of the MRS, which is similar to the DDR-I SDRAM operation. Seamless burst read or write operations are supported. Unlike DDR-I devices, interruption of a burst read or writes operation is limited to ready by Read or Write by Write at the boundary of Burst 4. Therefore the burst stop command is not supported on DDR2 SDRAM devices. [Burst Length and Sequence]
Burst length Starting address (A2, A1, A0) Sequential addressing (decimal) 000 4 001 010 011 000 001 010 8 011 100 101 110 111 0, 1, 2, 3 1, 2, 3, 0 2, 3, 0, 1 3, 0, 1, 2 0, 1, 2, 3, 4, 5, 6, 7 1, 2, 3, 0, 5, 6, 7, 4 2, 3, 0, 1, 6, 7, 4, 5 3, 0, 1, 2, 7, 4, 5, 6 4, 5, 6, 7, 0, 1, 2, 3 5, 6, 7, 4, 1, 2, 3, 0 6, 7, 4, 5, 2, 3, 0, 1 7, 4, 5, 6, 3, 0, 1, 2 Interleave addressing (decimal) 0, 1, 2, 3 1, 0, 3, 2 2, 3, 0, 1 3, 2, 1, 0 0, 1, 2, 3, 4, 5, 6, 7 1, 0, 3, 2, 5, 4, 7, 6 2, 3, 0, 1, 6, 7, 4, 5 3, 2, 1, 0, 7, 6, 5, 4 4, 5, 6, 7, 0, 1, 2, 3 5, 4, 7, 6, 1, 0, 3, 2 6, 7, 4, 5, 2, 3, 0, 1 7, 6, 5, 4, 3, 2, 1, 0
Note: Page length is a function of I/O organization and column addressing 8M bits x 8 organization (CA0 to CA9); Page Length = 1024 bits 4M bits x 16 organization (CA0 to CA8); Page Length = 512 bits
Preliminary Data Sheet E0515E12 (Ver. 1.2)
39
EDE2508AASE/16AASE-DF, -BE, -AE
Burst Read Command [READ] The Burst Read command is initiated by having /CS and /CAS low while holding /RAS and /WE high at the rising edge of the clock. The address inputs determine the starting column address for the burst. The delay from the start of the command to when the data from the first cell appears on the outputs is equal to the value of the read latency (RL). The data strobe output (DQS) is driven low 1 clock cycle before valid data (DQ) is driven onto the data bus. The first bit of the burst is synchronized with the rising edge of the data strobe (DQS). Each subsequent data-out appears on the DQ pin in phase with the DQS signal in a source synchronous manner. The RL is equal to an additive latency (AL) plus /CAS latency (CL). The CL is defined by the mode register set (MRS), similar to the existing SDR and DDR-I SDRAMs. The AL is defined by the extended mode register set (EMRS).
T0 /CK CK Command
READ
T1
T2
T3
T4
T5
T6
T7
T8
NOP
DQS, /DQS
CL = 3 RL = 3
DQ
out0 out1 out2 out3
Burst Read Operation (RL = 3, BL = 4 (AL = 0 and CL = 3))
T0 /CK CK Command
READ
T1
T2
T3
T4
T5
T6
T7
T8
NOP
DQS, /DQS
CL = 3 RL = 3
DQ
out0 out1 out2 out3 out4 out5 out6 out7
Burst Read Operation (RL = 3, BL = 8 (AL = 0 and CL = 3))
Preliminary Data Sheet E0515E12 (Ver. 1.2)
40
EDE2508AASE/16AASE-DF, -BE, -AE
T0 /CK CK Command
Posted READ NOP
T1
T2
T3
T4
T5
T6
T7
T8
DQS, /DQS
AL = 2 RL = 5 CL = 3
DQ
out0 out1 out2 out3
Burst Read Operation (RL = 5, BL = 4 (AL = 2, CL = 3))
T0 /CK CK Command
Posted READ
T1
T3
T4
T5
T6
T7
T8
T9
NOP
NOP
Posted WRIT
NOP
tRTW (Read to Write = 4 clocks)
DQS, /DQS
RL = 5
WL = RL - 1 = 4
DQ
out0 out1 out2 out3
in0
in1
in2
in3
Burst Read Followed by Burst Write (RL = 5, WL = RL-1 = 4, BL = 4) The minimum time from the burst read command to the burst write command is defined by a read-to-write-turnaround-time, which is 4 clocks.
T0 /CK CK Command
Posted READ
A
T1
T2
T3
T4
T5
T6
T7
T8
NOP
Posted READ
B
NOP
DQS, /DQS
AL = 2 CL = 3 RL = 5
DQ
out A0
out A1
out A2
out A3
out B0
out B1
out B2
Seamless Burst Read Operation (RL = 5, AL = 2, and CL = 3)
Preliminary Data Sheet E0515E12 (Ver. 1.2)
41
EDE2508AASE/16AASE-DF, -BE, -AE
Enabling a read command at every other clock supports the seamless burst read operation. This operation is allowed regardless of same or different banks as long as the banks are activated.
T0 /CK CK Command
READ
NOP
READ
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10
T11
NOP
A
B
DQS, /DQS
RL = 4
DQ
out A0
out A1
out A2
out A3
out B0
out out B1 B2
out B3
out B4
out B5
out B6
out B7
Burst interrupt is only allowed at this timing.
Burst Read Interrupt by Read Notes :1. Read burst interrupt function is only allowed on burst of 8. burst interrupt of 4 is prohibited. 2. Read burst of 8 can only be interrupted by another read command. Read burst interruption by write command or precharge command is prohibited. 3. Read burst interrupt must occur exactly two clocks after previous read command. any other read burst interrupt timings are prohibited. 4. Read burst interruption is allowed to any bank inside DRAM. 5. Read burst with auto precharge enabled is not allowed to interrupt. 6. Read burst interruption is allowed by another read with auto precharge command. 7. All command timings are referenced to burst length set in the mode register. They are not referenced to actual burst. For example, minimum read to precharge timing is AL + BL/2 where BL is the burst length set in the mode register and not the actual burst (which is shorter because of interrupt).
Preliminary Data Sheet E0515E12 (Ver. 1.2)
42
EDE2508AASE/16AASE-DF, -BE, -AE
Burst Write Command [WRIT] The Burst Write command is initiated by having /CS, /CAS and /WE low while holding /RAS high at the rising edge of the clock. The address inputs determine the starting column address. Write latency (WL) is defined by a read latency (RL) minus one and is equal to (AL + CL -1). A data strobe signal (DQS) should be driven low (preamble) one clock prior to the WL. The first data bit of the burst cycle must be applied to the DQ pins at the first rising edge of the DQS following the preamble. The tDQSS specification must be satisfied for write cycles. The subsequent burst bit data are issued on successive edges of the DQS until the burst length of 4 is completed. When the burst has finished, any additional data supplied to the DQ pins will be ignored. The DQ Signal is ignored after the burst write operation is complete. The time from the completion of the burst write to bank precharge is the write recovery time (tWR).
T0 /CK CK Command
WRIT
T1
T2
T3
T4
T5
T6
T7
T9
NOP
Completion of the Burst Write
PRE
NOP
ACT
DQS, /DQS
WL = RL -1 = 2
>tWR =
>tRP =
DQ
in0
in1
in2
in3
Burst Write Operation (RL = 3, WL = 2, BL = 4 tWR = 2 (AL=0, CL=3))
T0 /CK CK Command
WRIT
T1
T2
T3
T4
T5
T6
T7
T8
T9
T11
NOP
PRE
NOP
ACT
DQS, /DQS
WL = RL -1 = 2
>tWR =
>tRP =
DQ
in0
in1
in2
in3
in4
in5
in6
in7
Burst Write Operation (RL = 3, WL = 2, BL = 8 (AL=0, CL=3))
Preliminary Data Sheet E0515E12 (Ver. 1.2)
43
EDE2508AASE/16AASE-DF, -BE, -AE
T0 /CK CK Command
Posted WRIT NOP
T1
T2
T3
T4
T5
T6
T7
T9
PRE
DQS, /DQS
WL = RL -1 = 4 >tWR =
DQ
in0
in1
in2
in3
Burst Write Operation (RL = 5, WL = 4, BL = 4 tWR = 3 (AL=2, CL=3))
T0 /CK CK Command
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10
Write to Read = CL + 1 + tWTR (2) = 6
NOP
Posted READ
NOP
DQS, /DQS
AL = 2
WL = RL -1 = 4
CL = 3
RL = 5
>tWTR =
DQ
in0
in1
in2
in3
out0
out1
Burst Write Followed by Burst Read (RL = 5, BL = 4, WL = 4, tWTR = 2 (AL=2, CL=3)) The minimum number of clock from the burst write command to the burst read command is CL + 1 + a write to-readturn-around-time (tWTR). This tWTR is not a write recovery time (tWR) but the time required to transfer the 4bit write data from the input buffer into sense amplifiers in the array.
T0 /CK CK Command
Posted WRIT A
T1
T2
T3
T4
T5
T6
T7
T8
NOP
Posted WRIT B
NOP
DQS, /DQS
WL = RL - 1 = 4
DQ
in A0
in A1
in A2
in A3
in B0
in B1
in B2
in B3
Seamless Burst Write Operation (RL = 5, WL = 4, BL = 4) Enabling a write command every other clock supports the seamless burst write operation. This operation is allowed regardless of same or different banks as long as the banks are activated.
Preliminary Data Sheet E0515E12 (Ver. 1.2)
44
EDE2508AASE/16AASE-DF, -BE, -AE
T0 /CK CK Command
WRIT
NOP
WRIT
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10
T11
NOP
A
B
DQS, /DQS
WL = 3
DQ
in in in in A0 A1 A2 A3
in B0
in in in in in in B1 B2 B3 B4 B5 B6
in B7
Burst interrupt is only allowed at this timing.
Write Interrupt by Write (WL = 3, BL = 8) Notes :1. Write burst interrupt function is only allowed on burst of 8. Burst interrupt of 4 is prohibited. 2. Write burst of 8 can only be interrupted by another write command. Write burst interruption by read command or precharge command is prohibited. 3. Write burst interrupt must occur exactly two clocks after previous write command. Any other write burst interrupt timings are prohibited. 4. Write burst interruption is allowed to any bank inside DRAM. 5. Write burst with auto precharge enabled is not allowed to interrupt. 6. Write burst interruption is allowed by another write with auto precharge command. 7. All command timings are referenced to burst length set in the mode register. They are not referenced to actual burst. For example, minimum write to precharge timing is WL+BL/2+tWR where tWR starts with the rising clock after the un-interrupted burst end and not from the end of actual burst end.
Preliminary Data Sheet E0515E12 (Ver. 1.2)
45
EDE2508AASE/16AASE-DF, -BE, -AE
Write Data Mask One write data mask (DM) pin for each 8 data bits (DQ) will be supported on DDR2 SDRAMs, Consistent with the implementation on DDR-I SDRAMs. It has identical timings on write operations as the data bits, and though used in a uni-directional manner, is internally loaded identically to data bits to insure matched system timing. DM is not used during read cycles.
T1 DQS /DQS DQ
T2
T3
T4
T5
T6
in
in
in
in
in
in
in
in
DM Write mask latency = 0
Data Mask Timing
[tDQSS(min.)] /CK CK
tWR
Command
WRIT
WL
NOP
tDQSS
DQS, /DQS DQ DM
WL
in0
in2 in3
[tDQSS(max.)]
tDQSS
DQS, /DQS DQ DM
in0
in2 in3
Data Mask Function, WL = 3, AL = 0 shown
Preliminary Data Sheet E0515E12 (Ver. 1.2)
46
EDE2508AASE/16AASE-DF, -BE, -AE
Precharge Command [PRE] The precharge command is used to precharge or close a bank that has been activated. The precharge command is triggered when /CS, /RAS and /WE are low and /CAS is high at the rising edge of the clock. The precharge command can be used to precharge each bank independently or all banks simultaneously. Three address bits A10, BA0 and BA1 are used to define which bank to precharge when the command is issued. [Bank Selection for Precharge by Address Bits]
A10 L L L L H BA0 L H L H x BA1 L L H H x Precharged Bank(s) Bank 0 only Bank 1 only Bank 2 only Bank 3 only All banks 0 to 3
Remark: H: VIH, L: VIL, x: VIH or VIL Burst Read Operation Followed by Precharge Minimum read to precharge command spacing to the same bank = AL + BL/2 clocks For the earliest possible precharge, the precharge command may be issued on the rising edge that is "Additive latency (AL) + BL/2 clocks" after a Read command. A new bank active (command) may be issued to the same bank after the RAS precharge time (tRP). A precharge command cannot be issued until tRAS is satisfied.
/CK CK Command
Posted READ
T0
T1
T2
T3
T4
T5
T6
T7
T8
NOP
AL + 2 clocks
PRE
NOP
ACT
NOP
DQS, /DQS
AL = 1
CL = 3
> = tRP
RL = 4
DQ
> = tRAS
out0
out1
out2
out3
CL = 3
Burst Read Operation Followed by Precharge (RL = 4, BL = 4 (AL=1, CL=3))
/CK CK Command
T0
T1
T2
T3
T4
T5
T6
T7
T8
Posted READ
NOP
AL + 2 clocks
PRE
NOP
ACT
NOP
DQS, /DQS
AL = 2
CL = 3
> = tRP
RL = 5
DQ
> = tRAS
out0
out1
out2
out3
CL = 3
Burst Read Operation Followed by Precharge (RL = 5, BL = 4 (AL=2, CL=3))
Preliminary Data Sheet E0515E12 (Ver. 1.2)
47
EDE2508AASE/16AASE-DF, -BE, -AE
T0 /CK CK Command
Posted READ AL + BL/2 Clocks
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10
NOP
PRE
NOP
ACT
NOP
DQS, /DQS
AL = 2
RL = 6
CL = 4
>t = RP
DQ
>t = RAS(min.)
out0
out1
out2
out3
out4
out5
out6
out7
Burst Read Operation Followed by Precharge (RL = 6 (AL=2, CL=4, BL=8))
Preliminary Data Sheet E0515E12 (Ver. 1.2)
48
EDE2508AASE/16AASE-DF, -BE, -AE
Burst Write followed by Precharge Minimum Write to Precharge Command spacing to the same bank = WL + BL/2 clocks + tWR For write cycles, a delay must be satisfied from the completion of the last burst write cycle until the precharge command can be issued. This delay is known as a write recovery time (tWR) referenced from the completion of the burst write to the precharge command. No precharge command should be issued prior to the tWR delay, as DDR2 SDRAM allows the burst interrupt operation only Read by Read or Write by Write at the boundary of burst 4.
T0 /CK CK Command
Posted WRIT
T1
T2
T3
T4
T5
T6
T7
T8
NOP
PRE
> tWR =
DQS, /DQS
WL = 3
DQ
in0
in1
in2
in3
Completion of the Burst Write
Burst Write Followed by Precharge (WL = (RL-1) =3)
T0 /CK CK Command
Posted WRIT
T1
T2
T3
T4
T5
T6
T7
T9
NOP
PRE
> = tWR
DQS, /DQS
WL = 4
DQ
in0
in1
in2
in3
Completion of the Burst Write
Burst Write Followed by Precharge (WL = (RL-1) = 4)
T0 /CK CK Command
Posted WRIT
T1
T2
T3
T4
T5
T6
T7
T8
T9
T11
NOP
PRE
> = tWR
DQS, /DQS
WL = 4
DQ
in0
in1
in2
in3
in4
in5
in6
in7
Completion of the Burst Write
Burst Write Followed by Precharge (WL = (RL-1) = 4,BL= 8)
Preliminary Data Sheet E0515E12 (Ver. 1.2)
49
EDE2508AASE/16AASE-DF, -BE, -AE
Auto-Precharge Operation Before a new row in an active bank can be opened, the active bank must be precharged using either the precharge command or the auto-precharge function. When a read or a write command is given to the DDR2 SDRAM, the /CAS timing accepts one extra address, column address A10, to allow the active bank to automatically begin precharge at the earliest possible moment during the burst read or write cycle. If A10 is low when the read or write Command is issued, then normal read or write burst operation is executed and the bank remains active at the completion of the burst sequence. If A10 is high when the Read or Write Command is issued, then the auto-precharge function is engaged. During auto-precharge, a read Command will execute as normal with the exception that the active bank will begin to precharge on the rising edge which is /CAS latency (CL) clock cycles before the end of the read burst. Auto-precharge can also be implemented during Write commands. The precharge operation engaged by the Auto precharge command will not begin until the last data of the burst write sequence is properly stored in the memory array. This feature allows the precharge operation to be partially or completely hidden during burst read cycles (dependent upon /CAS latency) thus improving system performance for random data access. The /RAS lockout circuit internally delays the Precharge operation until the array restore operation has been completed so that the auto precharge command may be issued with any read or write command. Burst Read with Auto Precharge [READA] If A10 is high when a Read Command is issued, the Read with Auto-Precharge function is engaged. The DDR2 SDRAM starts an auto Precharge operation on the rising edge which is (AL + BL/2) cycles later from the read with AP command when the condition that. When tRAS (min) is satisfied. If tRAS (min.) is not satisfied at the edge, the start point so auto-precharge operation will be delayed until tRAS (min.) is satisfied. A new bank active (command) may be issued to the same bank if the following two conditions are satisfied simultaneously. (1) The /RAS precharge time (tRP) has been satisfied from the clock at which the auto precharge begins. (2) The /RAS cycle time (tRC) from the previous bank activation has been satisfied.
T0 /CK CK
A10 = 1
T1
T2
T3
T4
T5
T6
T7
T8
Command
Posted READ
> = tRAS(min.)
NOP
ACT
DQS, /DQS
> = tRP
AL = 2
CL = 3
RL = 5
DQ
> tRC =
out0
out1
out2
out3
CL = 3
Auto precharge begins
Burst Read with Auto Precharge Followed by an Activation to the Same Bank (tRC limit) (RL = 5, BL = 4 (AL = 2, CL = 3, internal tRCD = 3))
Preliminary Data Sheet E0515E12 (Ver. 1.2)
50
EDE2508AASE/16AASE-DF, -BE, -AE
T-1 /CK CK
A10 = 1
T0
T1
T2
T3
T4
T5
T6
T7
T8
Command
Posted READ
> = tRAS(min.)
NOP
ACT
DQS, /DQS
> = tRP
AL = 2
CL = 3
RL = 5
DQ
> tRC =
out0
out1
out2
out3
CL = 3
Auto precharge begins
Burst Read with Auto Precharge Followed by an Activation to the Same Bank (tRAS lockout case) (RL = 5, BL = 4 (AL = 2, CL = 3, internal tRCD = 3))
T0 /CK CK
A10 = 1
T1
T2
T3
T4
T5
T6
T7
T8
Command
Posted READ
> tRAS(min.) =
NOP
ACT
NOP
DQS, /DQS
> = tRP
AL = 2
CL = 3
RL = 5
DQ
> = tRC
out0
out1
out2
out3
CL = 3
Auto precharge begins
Burst Read with Auto Precharge Followed by an Activation to the Same Bank (tRP limit) (RL = 5, BL = 4 (AL = 2, CL = 3, internal tRCD = 3)
T0 /CK CK
A10 = 1
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10
T11
Command
READ
tRAS (min.)
NOP
ACT
DQS, /DQS
AL = 2 CL = 3
tRP
RL = 5
DQ
tRC
out0 out1 out2 out3 out4 out5 out6 out7
Auto Precharge begins
Burst Read with Auto Precharge Followed by an Activation to the Same Bank (RL = 5, BL = 8 (AL = 2, CL = 3)
Preliminary Data Sheet E0515E12 (Ver. 1.2)
51
EDE2508AASE/16AASE-DF, -BE, -AE
Burst Write with Auto-Precharge [WRITA] If A10 is high when a write command is issued, the Write with auto-precharge function is engaged. The DDR2 SDRAM automatically begins precharge operation after the completion of the burst writes plus write recovery time (tWR). The bank undergoing auto-precharge from the completion of the write burst may be reactivated if the following two conditions are satisfied. (1) The data-in to bank activate delay time (tWR + tRP) has been satisfied. (2) The /RAS cycle time (tRC) from the previous bank activation has been satisfied.
T0 /CK CK Command
A10 = 1
T1
T2
T3
T4
T5
T6
T7
T12
Posted WRIT
NOP
ACT
DQS, /DQS
WL = RL -1 = 2
> = tWR
in0
> = tRP
DQ
in1
in2
in3
> = tRC
Completion of the Burst Write
Auto Precharge Begins
Burst Write with Auto-Precharge (tRC Limit) (WL = 2, tWR =2, tRP=3)
T0 /CK CK Command
A10 = 1
T3
T4
T5
T6
T7
T8
T9
T10
Posted WRIT
NOP
NOP
ACT
DQS, /DQS
WL = RL -1 = 4
> = tWR
in0
in1
> = tRP
DQ
in2
in3
> = tRC
Completion of the Burst Write
Auto Precharge Begins
Burst Write with Auto-Precharge (tWR + tRP) (WL = 4, tWR =2, tRP=3)
Preliminary Data Sheet E0515E12 (Ver. 1.2)
52
EDE2508AASE/16AASE-DF, -BE, -AE
T0 /CK CK
A10 = 1
T2
T3
T4
T5
T6
T7
T8
T9
T10
T11
T12
T13
Command
WRIT
NOP
ACT
DQS, /DQS
WL = RL - 1 = 4
tWR tRP
DQ
tRC
in0
in1
in2
in3
in4
in5
in6
in7
Auto Precharge begins.
Burst Write with Auto Precharge Followed by an Activation to the Same Bank (WL = 4, BL = 8, tWR = 2, tRP = 3)
Preliminary Data Sheet E0515E12 (Ver. 1.2)
53
EDE2508AASE/16AASE-DF, -BE, -AE
Refresh Requirements DDR2 SDRAM requires a refresh of all rows in any rolling 64ms interval. Each refresh is generated in one of two ways: by an explicit automatic refresh command, or by an internally timed event in self-refresh mode. Dividing the number of device rows into the rolling 64 ms interval defines the average refresh interval, tREFI, which is a guideline to controllers for distributed refresh timing. Automatic Refresh Command [REF] When /CS, /RAS and /CAS are held low and /WE high at the rising edge of the clock, the chip enters the automatic refresh mode (REF). All banks of the DDR2 SDRAM must be precharged and idle for a minimum of the precharge time (tRP) before the auto refresh command (REF) can be applied. An address counter, internal to the device, supplies the bank address during the refresh cycle. No control of the external address bus is required once this cycle has started. When the refresh cycle has completed, all banks of the DDR2 SDRAM will be in the precharged (idle) state. A delay between the auto refresh command (REF) and the next activate command or subsequent auto refresh command must be greater than or equal to the auto refresh cycle time (tRFC). To allow for improved efficiency in scheduling and switching between tasks, some flexibility in the absolute refresh interval is provided. A maximum of 8 refresh commands can be posted to any given DDR2 SDRAM, meaning that the maximum absolute interval between any refresh command and the next Refresh command is 9 x tREFI.
T0 /CK CK
VIH
T1
T2
T3
T15
T7
T8
CKE
tRP
tRFC
tRFC
Command
PRE
NOP
REF
REF
NOP
Any Command
Automatic Refresh Command
Preliminary Data Sheet E0515E12 (Ver. 1.2)
54
EDE2508AASE/16AASE-DF, -BE, -AE
Self Refresh Command [SELF] The DDR2 SDRAM device has a built-in timer to accommodate self-refresh operation. The self-refresh command is defined by having /CS, /RAS, /CAS and CKE held low with /WE high at the rising edge of the clock. ODT must be turned off before issuing self refresh command, by either driving ODT pin low or using EMRS command. Once the command is registered, CKE must be held low to keep the device in self-refresh mode. When the DDR2 SDRAM has entered self refresh mode all of the external signals except CKE, are "don't care". The clock is internally disabled during self-refresh operation to save power. The user may change the external clock frequency or halt the external clock one clock after Self-Refresh entry is registered, however, the clock must be restarted and stable before the device can exit self refresh operation. Once self-refresh exit command is registered, a delay equal or longer than the tXSNR or tXSRD must be satisfied before a valid command can be issued to the device. CKE must remain high for the entire self-refresh exit period tXSRD for proper operation. NOP or deselect commands must be registered on each positive clock edge during the self-refresh exit interval. ODT should also be turned off during tXSRD.
T0 T1 T2 T3 T4 T5 T6 Tm Tn
tCK
tCH tCL /CK CK tXSNR tRP* tXSRD CKE tIS tAOFD ODT tIS tIS
tIS tIH
Comand
SELF NOP
NOP
NOP
Valid
Notes: 1. Device must be in the "All banks idle" state prior to entering self refresh mode. 2. ODT must be turned off tAOFD before entering self refresh mode, and can be turned on again when tXSRD timing is satisfied. 3. tXSRD is applied for a read or a read with autoprecharge command. 4. tXSNR is applied for any command except a read or a read with autoprecharge command.
Self Refresh Command
Preliminary Data Sheet E0515E12 (Ver. 1.2)
55
EDE2508AASE/16AASE-DF, -BE, -AE
Power-Down [PDEN] Power-down is synchronously entered when CKE is registered low (along with NOP or deselect command). CKE is not allowed to go low while mode register or extended mode register command time, or read or write operation is in progress. CKE is allowed to go low while any of other operations such as row activation, precharge or autoprecharge, or auto-refresh is in progress, but power-down IDD spec will not be applied until finishing those operations. Timing diagrams are shown in the following pages with details for entry into power down. The DLL should be in a locked state when power-down is entered. Otherwise DLL should be reset after exiting power-down mode for proper read operation. If power-down occurs when all banks are idle, this mode is referred to as precharge power-down; if power-down occurs when there is a row active in any bank, this mode is referred to as active power-down. Entering power-down deactivates the input and output buffers, excluding CK, /CK, ODT and CKE. Also the DLL is disabled upon entering precharge power-down or slow exit active power-down, but the DLL is kept enabled during fast exit active powerdown. In power-down mode, CKE low and a stable clock signal must be maintained at the inputs of the DDR2 SDRAM, and ODT should be in a valid state but all other input signals are "Don't Care". CKE low must be maintained until tCKE has been satisfied. Power-down duration is limited by 9 times tREFI of the device. The power-down state is synchronously exited when CKE is registered high (along with a NOP or deselect command). CKE high must be maintained until tCKE has been satisfied. A valid, executable command can be applied with power-down exit latency, tXP, tXARD, or tXARDS, after CKE goes high. Power-down exit latency is defined at AC Characteristics table of this data sheet.
CK /CK CKE tIS tIH tIS tIH tIH tIS tIH tIS tIH
Command
VALID
NOP
NOP
VALID
VALID
VALID
tCKE
tCKE
tXP, tXARD, tXARDS tCKE Exit power-down mode VIH or VIL
Enter power-down mode
Power Down Read to Power-Down Entry
T0 /CK CK Command
VIH
READ
T1
T2
Tx
Tx+1
Tx+2
Tx+3
Tx+4
Tx+5
Tx+6
Tx+7
Tx+8
Tx+9
Read operation starts with a read command and CKE should be kept high until the end of burst operation.
CKE
DQS /DQS
AL + CL
DQ
out 0
out 1
out 2
out 3
BL=4
T0
T1
T2
Tx
Tx+1
Tx+2
Tx+3
Tx+4
Tx+5
Tx+6
Tx+7
Tx+8
Tx+9
Command
VIH
READ
CKE should be kept high until the end of burst operation.
CKE DQS /DQS
AL + CL
DQ
out 0
out out 1 2
out 3
out 4
out out 5 6
out 7
BL=8
Preliminary Data Sheet E0515E12 (Ver. 1.2)
56
EDE2508AASE/16AASE-DF, -BE, -AE
Read with Auto Precharge to Power-Down Entry
T0 /CK CK Command CKE
DQS /DQS DQ
AL + CL
out 0 out 1 out 2 out 3
T1
T2
Tx
Tx+1
Tx+2
Tx+3
Tx+4
Tx+5
Tx+6
Tx+7
Tx+8
Tx+9
READ
PRE
BL=4
AL + BL/2 with tRTP = 7.5ns and tRAS min. satisfied
CKE should be kept high until the end of burst operation.
T0
T1
T2
Tx
Tx+1
Tx+2
Tx+3
Tx+4
Tx+5
Tx+6
Tx+7
Tx+8
Tx+9
Start internal precharge
Command
CKE DQS /DQS
READ
BL=8
AL + BL/2 with tRTP = 7.5ns and tRAS min. satisfied
PRE
CKE should be kept high until the end of burst operation.
AL + CL
DQ
out 0
out 1
out 2
out 3
out 4
out out 5 6
out 7
Write to Power-Down Entry
T0 T1 Tm Tm+1 Tm+2 Tm+3 Tx Tx+1 Tx+2 Ty Ty+1 Ty+2 Ty+3
/CK CK Command CKE
tWTR
WRIT
DQS /DQS
DQ
WL
in 0 in 1 in 2 in 3
BL=4
T0
T1
Tm
Tm+1
Tm+2 Tm+3
Tm+4 Tm+5
Tx
Tx+1
Tx+2
Tx+3
Tx+4
Command
CKE
WRIT
tWTR
DQS /DQS DQ
WL
in 0 in 1 in 2 in 3 in 4 in 5 in 6 in 7
BL=8
Preliminary Data Sheet E0515E12 (Ver. 1.2)
57
EDE2508AASE/16AASE-DF, -BE, -AE
Write with Auto Precharge to Power-Down Entry
T0 T1 Tm Tm+1 Tm+2 Tm+3 Tx Tx+1 Tx+2 Tx+3 Tx+4 Tx+5 Tx+6
/CK CK Command
WRITA
PRE
CKE
DQS /DQS DQ
WR*1
WL
in 0 in 1 in 2 in 3
BL=4
T0
T1
Tm
Tm+1
Tm+2
Tm+3
Tm+4
Tm+5
Tx
Tx+1
Tx+2
Tx+3
Tx+4
/CK CK
Command
WRITA
PRE
CKE DQS /DQS DQ
WR*1
WL
in 0 in 1 in 2 in 3 in 4 in 5 in 6 in 7
BL=8
Note: 1. WR is programmed through MRS
Preliminary Data Sheet E0515E12 (Ver. 1.2)
58
EDE2508AASE/16AASE-DF, -BE, -AE
Refresh command to Power-Down Entry
T0 /CK CK Command CKE
REF
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10
T11
CKE can go to low one clock after an auto-refresh command
Active command to power down entry
Command CKE
ACT
CKE can go to low one clock after an active command
Precharge/Precharge all command to power down entry
Command CKE
PRE or PALL
CKE can go to low one clock after a precharge or precharge all command
MRS/EMRS command to power down entry
Command
MRS or EMRS
CKE
tMRD
Preliminary Data Sheet E0515E12 (Ver. 1.2)
59
EDE2508AASE/16AASE-DF, -BE, -AE
Asynchronous CKE Low Event DRAM requires CKE to be maintained high for all valid operations as defined in this data sheet. If CKE asynchronously drops low during any valid operation DRAM is not guaranteed to preserve the contents of array. If this event occurs, memory controller must satisfy DRAM timing specification tDELAY before turning off the clocks. Stable clocks must exist at the input of DRAM before CKE is raised high again. DRAM must be fully re-initialized (steps 4 through 13) as described in initialization sequence. DRAM is ready for normal operation after the initialization sequence. See AC Characteristics table for tDELAY specification
tCK /CK CK CKE tDELAY Stable clocks
CKE asynchronously drops low
Clocks can be turned off after this point
Preliminary Data Sheet E0515E12 (Ver. 1.2)
60
EDE2508AASE/16AASE-DF, -BE, -AE
Input Clock Frequency Change during Precharge Power Down DDR2 SDRAM input clock frequency can be changed under following condition: DDR2 SDRAM is in precharged power down mode. ODT must be turned off and CKE must be at logic low level. A minimum of 2 clocks must be waited after CKE goes low before clock frequency may change. SDRAM input clock frequency is allowed to change only within minimum and maximum operating frequency specified for the particular speed grade. During input clock frequency change, ODT and CKE must be held at stable low levels. Once input clock frequency is changed, stable new clocks must be provided to DRAM before precharge power down may be exited and DLL must be RESET via EMRS after precharge power down exit. Depending on new clock frequency an additional MRS command may need to be issued to appropriately set the WR, CL and soon. During DLL relock period, ODT must remain off. After the DLL lock time, the DRAM is ready to operate with new clock frequency. Clock Frequency Change in Precharge Power Down Mode
T0 /CK CK Command CKE
NOP
NOP
NOP
NOP
DLL RESET
NOP
Valid
T1
T2
T4
Tx
Tx+1
Ty
Ty+1
Ty+2 Ty+3
Ty+4
Tz
Frequency change occurs here
200 clocks
ODT
tRP tAOFD tXP
Minmum 2 clocks required before changing frequency
ODT is off during DLL RESET Stable new clock before power down exit
Burst Interruption Interruption of a burst read or write cycle is prohibited. No Operation Command [NOP] The no operation command should be used in cases when the DDR2 SDRAM is in an idle or a wait state. The purpose of the no operation command is to prevent the DDR2 SDRAM from registering any unwanted commands between operations. A no operation command is registered when /CS is low with /RAS, /CAS, and /WE held high at the rising edge of the clock. A no operation command will not terminate a previous operation that is still executing, such as a burst read or write cycle. Deselect Command [DESL] The deselect command performs the same function as a no operation command. Deselect Command occurs when /CS is brought high at the rising edge of the clock, the /RAS, /CAS, and /WE signals become don't cares.
Preliminary Data Sheet E0515E12 (Ver. 1.2)
61
EDE2508AASE/16AASE-DF, -BE, -AE
Package Drawing
64-ball FBGA Solder ball: Lead free (Sn-Ag-Cu)
Unit: mm
11.3 0.1
INDEX MARK
0.2 S B
13.8 0.1
0.2 S A 0.2 S
1.12 max.
S
0.35 0.05
0.1 S
2.45
1.6
0.8
B
1.3
0.8
A
INDEX MARK
3.2
64-0.45 0.05
0.08 M S A B
ECA-TS2-0091-01
Preliminary Data Sheet E0515E12 (Ver. 1.2)
62
EDE2508AASE/16AASE-DF, -BE, -AE
84-ball FBGA Solder ball: Lead free (Sn-Ag-Cu)
Unit: mm
11.3 0.1
INDEX MARK
0.2 S B
13.8 0.1
0.2 S A
0.2 S
1.12 max.
S
0.1 S
B
0.35 0.05
A
INDEX MARK
0.8
2.45
1.6
0.8
1.3
84-0.45 0.05
0.08 M S A B
ECA-TS2-0092-01
Preliminary Data Sheet E0515E12 (Ver. 1.2)
63
EDE2508AASE/16AASE-DF, -BE, -AE
Recommended Soldering Conditions
Please consult with our sales offices for soldering conditions of the EDE25XXAASE. Type of Surface Mount Device EDE2508AASE: 64-ball FBGA < Lead free (Sn-Ag-Cu) > EDE2516AASE 84-ball FBGA < Lead free (Sn-Ag-Cu) >
Preliminary Data Sheet E0515E12 (Ver. 1.2)
64
EDE2508AASE/16AASE-DF, -BE, -AE
NOTES FOR CMOS DEVICES
1 PRECAUTION AGAINST ESD FOR MOS DEVICES
Exposing the MOS devices to a strong electric field can cause destruction of the gate oxide and ultimately degrade the MOS devices operation. Steps must be taken to stop generation of static electricity as much as possible, and quickly dissipate it, when once it has occurred. Environmental control must be adequate. When it is dry, humidifier should be used. It is recommended to avoid using insulators that easily build static electricity. MOS devices must be stored and transported in an anti-static container, static shielding bag or conductive material. All test and measurement tools including work bench and floor should be grounded. The operator should be grounded using wrist strap. MOS devices must not be touched with bare hands. Similar precautions need to be taken for PW boards with semiconductor MOS devices on it.
2 HANDLING OF UNUSED INPUT PINS FOR CMOS DEVICES
No connection for CMOS devices input pins can be a cause of malfunction. If no connection is provided to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence causing malfunction. CMOS devices behave differently than Bipolar or NMOS devices. Input levels of CMOS devices must be fixed high or low by using a pull-up or pull-down circuitry. Each unused pin should be connected to VDD or GND with a resistor, if it is considered to have a possibility of being an output pin. The unused pins must be handled in accordance with the related specifications.
3 STATUS BEFORE INITIALIZATION OF MOS DEVICES
Power-on does not necessarily define initial status of MOS devices. Production process of MOS does not define the initial operation status of the device. Immediately after the power source is turned ON, the MOS devices with reset function have not yet been initialized. Hence, power-on does not guarantee output pin levels, I/O settings or contents of registers. MOS devices are not initialized until the reset signal is received. Reset operation must be executed immediately after power-on for MOS devices having reset function.
CME0107
Preliminary Data Sheet E0515E12 (Ver. 1.2)
65
EDE2508AASE/16AASE-DF, -BE, -AE
The information in this document is subject to change without notice. Before using this document, confirm that this is the latest version.
No part of this document may be copied or reproduced in any form or by any means without the prior written consent of Elpida Memory, Inc. Elpida Memory, Inc. does not assume any liability for infringement of any intellectual property rights (including but not limited to patents, copyrights, and circuit layout licenses) of Elpida Memory, Inc. or third parties by or arising from the use of the products or information listed in this document. No license, express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of Elpida Memory, Inc. or others. Descriptions of circuits, software and other related information in this document are provided for illustrative purposes in semiconductor product operation and application examples. The incorporation of these circuits, software and information in the design of the customer's equipment shall be done under the full responsibility of the customer. Elpida Memory, Inc. assumes no responsibility for any losses incurred by customers or third parties arising from the use of these circuits, software and information. [Product applications] Elpida Memory, Inc. makes every attempt to ensure that its products are of high quality and reliability. However, users are instructed to contact Elpida Memory's sales office before using the product in aerospace, aeronautics, nuclear power, combustion control, transportation, traffic, safety equipment, medical equipment for life support, or other such application in which especially high quality and reliability is demanded or where its failure or malfunction may directly threaten human life or cause risk of bodily injury. [Product usage] Design your application so that the product is used within the ranges and conditions guaranteed by Elpida Memory, Inc., including the maximum ratings, operating supply voltage range, heat radiation characteristics, installation conditions and other related characteristics. Elpida Memory, Inc. bears no responsibility for failure or damage when the product is used beyond the guaranteed ranges and conditions. Even within the guaranteed ranges and conditions, consider normally foreseeable failure rates or failure modes in semiconductor devices and employ systemic measures such as fail-safes, so that the equipment incorporating Elpida Memory, Inc. products does not cause bodily injury, fire or other consequential damage due to the operation of the Elpida Memory, Inc. product. [Usage environment] This product is not designed to be resistant to electromagnetic waves or radiation. This product must be used in a non-condensing environment. If you export the products or technology described in this document that are controlled by the Foreign Exchange and Foreign Trade Law of Japan, you must follow the necessary procedures in accordance with the relevant laws and regulations of Japan. Also, if you export products/technology controlled by U.S. export control regulations, or another country's export control laws or regulations, you must follow the necessary procedures in accordance with such laws or regulations. If these products/technology are sold, leased, or transferred to a third party, or a third party is granted license to use these products, that third party must be made aware that they are responsible for compliance with the relevant laws and regulations.
M01E0107
Preliminary Data Sheet E0515E12 (Ver. 1.2)
66

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